DS616 Datasheet, PDF (23/60 Pages) Xilinx, Inc – LogiCORE IP PLBV46 PCI Full

LogiCORE IP PLBV46 PCI Full Bridge (v1.04.a)
Register and Parameter Dependencies
The addressable registers in the PLBV46 PCI Bridge depend on the parameter settings shown in Table 6.
Table 6: Register and Parameter Dependencies
Register Name
Parameter Dependence
Device Interrupt Status Register (ISR)
Always present
Device Interrupt Pending Register (IPR)
Always present
Device Interrupt Enable Register (IER)
Always present
Device Interrupt ID (IID)
Always present
Global Interrupt Enable Register (GIE)
Always present
Bridge Interrupt Register
Always present
Bridge Interrupt Enable Register
Always present
Reset Module
Always present
Configuration Address Port
Present only if G61=1
Configuration Data Port
Present only if G61=1
Bus Number/Subordinate Bus Number
Present only if G61=1
IPIFBAR2PCIBAR_0 High-Order Bits
Present only if G45=1
IPIFBAR2PCIBAR_1 High-Order Bits
Present only if G1>1 and G45=1
IPIFBAR2PCIBAR_2 High-Order Bits
Present only if G1>2 and G45=1
IPIFBAR2PCIBAR_3 High-Order Bits
Present only if G1>3 and G45=1
IPIFBAR2PCIBAR_4 High-Order Bits
Present only if G1>4 and G45=1
IPIFBAR2PCIBAR_5 High-Order Bits
Present only if G1=6 and G45=1
Host Bridge Device Number
Present only if G46=1
PLBV46 PCI Bridge Interrupt Registers Descriptions
The interrupt module registers are always included in the bridge.
Interrupt Module Specifications
The interrupt registers are in the interrupt module that is instantiated in the IPIF module of the PLBV46 PCI Bridge.
Device Interrupt Status Register (DISR)
The Device Interrupt Status Register gives the interrupt status for the device (IPIF + Bridge Interrupts). Each bit
within this register represents a major function within the device. The bits are detailed in Table 7. This register is
fixed at 32 bits wide and each utilized bit within the register is set to ’1’ whenever the corresponding interrupt input
has met the interrupt capture criteria. Unlike the Bridge Interrupt Status Register, the interrupt capture mode for
this register is fixed. The DPTO and TERR bits are captured with a ’sample and hold high’ mode. This means that
if the input interrupt is sampled to be ’1’ at a rising edge of a PLB Clock pulse, the register bit is set to a ’1’ and ’held’
until the User Interrupt Service Routine clears it to a ’0’. The remaining bits within the register (IPIR) are pass
through. When asserted, they are ’held’ by the source of the interrupt (Bridge ISR) and therefore an additional
sample and hold operation is not necessary in this register. These interrupts must be cleared at the source function.
DS616 June 22, 2011
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