DS616 Datasheet, PDF (27/60 Pages) Xilinx, Inc – LogiCORE IP PLBV46 PCI Full

LogiCORE IP PLBV46 PCI Full Bridge (v1.04.a)
Table 12: Bridge Interrupt Register Bit Definitions (Bit Assignment Assumes 32-bit Bus) (Cont’d)
Bit(s)
Name
Access
Reset
Value
Description
23 PLB Master Write Read/Write 1
Retry Disconnect to toggle
0x0 PLB Master Burst Write Retry Disconnect- Interrupt(23)
indicates the automatic PCI write retries were not successful due to
a target disconnect on the last retry during a PLB Master burst write
to a PCI target.
24 PLB Master Write Read/Write 1
Retry
to toggle
0x0 PLB Master Write Retry- Interrupt(24) indicates the automatic PCI
write retries were not successful due to a PCI retry on the last retry
during a PLB Master burst write to a PCI target.
25 PLB Master Write Read/Write 1
Master Abort
to toggle
0x0 PLB Master Write Master Abort- Interrupt(25) indicates that the
PLBV46 PCI Bridge asserted a PCI master abort due to no
response from a target.
26 PLB Master Write Read/Write 1
Target Abort
to toggle
0x0 PLB Master Write Target Abort- Interrupt(26) indicates a PCI
target abort occurred during a PLB Master Write to a PCI target.
27 PLB Master Write Read/Write 1
PERR
to toggle
0x0 PLB Master Write PERR- Interrupt(27) indicates a PERR error is
detected on a PLB Master write to a PCI target.
28 PLB Master Write Read/Write 1
0x0 PLB Master Write SERR- Interrupt(28) indicates that a SERR error
SERR
to toggle
was detected by the PCI32 core when performing as a PCI initiator
writing data to a PCI target.
29 PLB Master Read Read/Write 1
0x0 PLB Master Read Target Abort- Interrupt(29) indicates that a
Target Abort
to toggle
target abort was detected by the PCI32 core when performing as a
PCI initiator reading data from a PCI target.
30 PLB Master Read Read/Write 1
0x0 PLB Master Read PERR- Interrupt(30) indicates that a PERR was
PERR
to toggle
detected by thePCI32 core when performing as a PCI initiator
reading data from a PCI target.
31 PLB Master Read Read/Write 1
0x0 PLB Master Read SERR- Interrupt(31) indicates that a SERR error
SERR
to toggle
was detected by the PCI32 core when performing as a PCI initiator
reading data from a PCI target.
Bridge Interrupt Enable Register Description
The PLBV46 PCI Bridge has interrupt enable features as described in IPSPEC048 PLB Device Interrupt Architecture.
Bit assignment in the Bridge Interrupt Enable Register is shown in Table 13. The interrupt enable register is
read/write. All bits are cleared upon reset.
Table 13: Bridge Interrupt Enable Register Bit Definitions (Bit assignment assumes 32-bit bus)
Bit(s)
Name
Access
0-14
15
PLB Read Slave
BAR Overrun
Read
Read/Write
Reset
Value
0x0
0x0
Description
Unassigned
PLB Read Slave BAR Overrun Enable- Enables this interrupt to be
passed to the interrupt controller.
• 0 - Not enabled.
• 1 - Enabled.
16 PLB Write Slave Read/Write
BAR Overrun
0x0 PLB Write Slave BAR Overrun Enable- Enables this interrupt to be
passed to the interrupt controller.
• 0 - Not enabled.
• 1 - Enabled.
DS616 June 22, 2011
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Product Specification