DS616 Datasheet, PDF (47/60 Pages) Xilinx, Inc – LogiCORE IP PLBV46 PCI Full

LogiCORE IP PLBV46 PCI Full Bridge (v1.04.a)
Table 25: Results of PCI32 core Command Register configuration by remote host bridge (PCI-side) and by
self-configuration (PLB-side) Note: Results for Virtex-5 FPGA self-configuration is the same as remote
host bridge configuration
Results in Command Register after write
(PLB-side byte swapped format)
Data Written (PLB-side byte
swapped format)
by remote host bridge (Virtex-4, Virtex-5
and Spartan-3) and by self-configuration
(Virtex-5)
by self-configuration (Virtex-4 and
Spartan-3)
0x0000
0x0000
0x4605
0x0100
0x0000
0x4605
0x0200
0x0200
0x4605
0x0300
0x0200
0x4605
0x0400
0x0400
0x4605
0x0500
0x0400
0x4605
0x8600
0x0600
0x4605
0x8700
0x0600
0x4605
0xFFFF
0x4605
0x4605
Note:
1. This assumes that the PCI BARs in the PCI32 core are configured to only Memory type and not I/O-type which is not an allowed
configuration. After self-configuration, a remote initiator can reconfigure the PCI32 core to any valid state.
Table 26: Results of PCI32 core Latency Timer Register configuration by remote host bridge (PCI-side)
and by self-configuration (PLB-side) Note: Results for Virtex-5 FPGA self-configuration same as remote
host bridge configuration
Results in Latency Timer Register after write
(PLB-side byte swapped format)
Data Written
by remote host bridge (Virtex-4, Virtex-5 and
Spartan-3) and by self-configuration
(Virtex-5)
by self-configuration (Virtex-4 and
Spartan-3)
0x00
0x00
0xFF
0x01
0x01
0xFF
0xFF
0xFF
0xFF
Table 25 and Table 26 show examples only and do not show all the possible bit patterns. The bytes are swapped for
maintaining byte addressing integrity.
The PCI32 core is PCI 2.2 compliant core, but it has PCI 2.3 compliant features. The PCI32 core documentation
should be reviewed for details of compliance.
Configuration transactions from the PLB-side of the bridge are supported by the PLBV46 PCI Bridge. The protocol
follows the PCI 2.2 specification but with changes required to adapt to the PLB-side bus protocol. The primary
difference is that all registers (Configuration Address Port, Configuration Data Port, and Bus Number/Subordinate
Bus Number) are on the PLB-side of the bridge and are not accessible from the PCI-side via I/O transactions on the
PCI bus. This approach is adopted so that one BAR of the PCI32 core is not required for the Configuration Port
registers. The registers are mapped relative to the bridge device base address as shown in Table 5. The registers exist
only if the bridge is configured with PCI host bridge configuration functionality.
DS616 June 22, 2011
www.xilinx.com
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Product Specification