DS616 Datasheet, PDF (33/60 Pages) Xilinx, Inc – LogiCORE IP PLBV46 PCI Full

LogiCORE IP PLBV46 PCI Full Bridge (v1.04.a)
Host Bridge Device Number Register Description
The Host Bridge Device Number register is included by setting C_INCLUDE_DEVNUM_REG=1. The register can
be included only if configuration functionality, such as C_INCLUDE_PCI_CONFIG=1, is included.
This register is read/write and is four bits wide. Table 18 shows specifics of the data format. The programmability
of this register allows programmable definition of the bridge device number and corresponding address bit that is
internally connected to its IDSEL signal. The maximum value that can be loaded in this register is given by the value
set by parameter C_NUM_IDSEL minus 1 because the device number must be consistent with the number of
devices that are supported in configuration transactions.
Table 18: Host Bridge Device Number (Bit assignment assumes 32-bit bus)
Bit(s)
Name
Access
Reset
Value
Description
0-27
D0-D27
Read Only
0x0
Set to zero.
28-31
D28 - D31
Read/Write
0x0
Defines the device number of the PLBV46 PCI Bridge when
configured as a Host Bridge.
PLB PCI Transactions
The following subsections discuss details of the following types of transactions for the PLBV46 PCI Bridge to realize
data throughputs as high as 132 MB/sec. This assumes the PLB clock is 100 MHz or higher. Lower data rates are
realized with lower PLB clock rates for some transactions.
• The section, PLB Master Initiates a Read Request of a PCI Target, discusses the PLB master read of a PCI target
where the PCI32 core is the PCI initiator.
• The section, PLB Master Initiates a Write Request to a PCI Target, discusses the PLB master write to a PCI
target where the PCI32 core is the PCI initiator.
• The section, PCI Initiator Initiates a Read Request of a PLB Slave, discusses the remote PCI initiator read of a
PLB device where the PCI32 core is the PCI target
• The section, PCI Initiator Initiates a Write Request to a PLB Slave, discusses the remote PCI initiator write to a
PLB device where the PCI32 core is the PCI target.
• The section, Configuration Transactions, discusses PLB master read and write of a PCI target configuration
space where the PCI32 core is the PCI initiator.
PLB transactions that are supported are limited to the subset of PLB transactions that are supported by the IPIF. This
limitation is caused by the time-multiplexed architecture of the PCI bus where addressing is required to be
incremented by 4 bytes per data phase. When operating as a master, the IPIF can either perform single transactions
(1-4 bytes) or bursts of an arbitrary length. In the case of writes, the length is determined by the PCI initiator
supplying the data and/or by how fast the PCI initiator supplies the data. In the case of reads, the length is
determined by either a parameterized number or up to the range limit of the PCI BAR, whichever is less. When the
IPIF is operating as a PLB slave, it performs single transfers of 1-4 bytes, burst transfers of any number of words,
and 4, 8 or 16-word line transactions. The IPIF always performs line read requests on the IPIC with the address
double word aligned, independent of the target word requested.
This is required because the PCI time-multiplexed address and data bus requires sequential addressing. PCI
commands that are supported include I/O read, I/O write, memory read, memory write, memory read multiple,
memory read line, and memory write invalidate. Table 19 shows the translations of PLB transactions to PCI
commands, while in Table 20 shows the translations of PCI commands to PLB transactions.
DS616 June 22, 2011
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Product Specification