DS616 Datasheet, PDF (1/60 Pages) Xilinx, Inc – LogiCORE IP PLBV46 PCI Full

DS616 June 22, 2011
LogiCORE IP PLBV46 PCI Full
Bridge (v1.04.a)
0
Product Specification
Introduction
The PLBV46 PCI™ Full Bridge design provides full
bridge functionality between the Xilinx® PLB and a
32-bit Revision 2.2 compliant Peripheral Component
Interconnect (PCI™) bus. The bridge is referred to as
the PLBV46 PCI Bridge in this document.
The Xilinx PLB is a 32, 64 or 128-bit bus subset of the
IBM PLB described in the 128-Bit Processor Local Bus
Architecture Specification v4.6.
The LogiCORE™ IP PCI32 core provides an interface
with the PCI bus. Details of the LogiCORE IP PCI32
core operation is found in the Xilinx LogiCORE PCI32
Interface v3, in the Xilinx LogiCORE PCI32 Interface v4
Product Specification, and in the Xilinx LogiCORE PCI
v3.0 and v4.1 User Guides.
Host bridge functionality (often called North bridge
functionality) is an optional functionality.
Configuration Read and Write PCI commands can be
performed from the PLB-side of the bridge. The
PLBV46 PCI Bridge supports a 32-bit/33 MHz PCI bus
only.
Exceptions to the support of PCI commands supported
by the PCI32 core are outlined in the Features section.
The PLBV46 PCI Bridge design has parameters that
allow customers to configure the bridge to suit their
application. The parameterizable features of the design
are discussed in the Bus Interface Parameters section.
LogiCORE IP Facts Table
Core Specifics
Supported
Device Family¹
Virtex-4, Virtex-5
Spartan-3, Spartan-6
Supported User
Interfaces
plbv46, pci
Resources
LUTs FFs
I/O
(PCI)
I/O
(PLB
related)
Block
RAMs
See Table 29.
Provided with Core
Documentation
Product Specification
Design Files
VHDL
Example Design
Not Provided
Test Bench
Not Provided
Constraints File
example UCF-file
Simulation
Model
Not Provided
Tested Design Tools
Design Entry
Tools
Simulation
ISE v13.2 software
Mentor Graphics ModelSim ²
Synthesis Tools
Support
Provided by Xilinx, Inc.
XST 13.2
1. For a complete listing of supported devices, see IDS Embedded
Edition Derivative Device Support for this core.
2. For the supported versions of the tools, see the ISE Design Suite
13: Release Notes Guide.
© Copyright 2007-2011 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks of
Xilinx in the United States and other countries. PCI, PCIe and PCI Express are trademarks of PCI-SIG and used under license. All other trademarks are the property
of their respective owners.
DS616 June 22, 2011
www.xilinx.com
1
Product Specification