DS616 Datasheet, PDF (41/60 Pages) Xilinx, Inc – LogiCORE IP PLBV46 PCI Full

LogiCORE IP PLBV46 PCI Full Bridge (v1.04.a)
Table 22 summarizes the abnormal conditions that a PCI target can respond with and how the response is translated
to the PLB master.
Table 22: Response of PLB Master/PCI Initiator write to a remote PCI target with abnormal condition on
PCI bus
Abnormal
Condition
Single Transfer
Burst
(PLB_wrBurst asserted)
SERR (includes
parity error on
address phase)
PLB Master Write SERR interrupt asserted If transfer is in progress, Sl_MWrErr is asserted with
Sl_wrDAck. PLB Master Write SERR interrupt asserted
PLBV46 PCI Bridge PLB Master Abort Write interrupt asserted
Master abort (no
PCI target
response)
If transfer is in progress, Sl_MWrErr is asserted with
Sl_wrDAck. PLB Master Abort Write interrupt is asserted
and the FIFO is flushed.
Target disconnect
without data (PCI
Retry)
Automatically retried a parameterized number
of times. If the last of the PCI write command
retries fails due to a PCI Retry, the PLB Master
Write Retry interrupt is asserted.
Automatically retried a parameterized number of times. If
the last of the PCI write command retries fails due to a
PCI Retry, the PLB Master Write Retry interrupt is
asserted.
Target disconnect N/A
without data (after
one completed data
phase)
Automatically retried a parameterized number of times. If
the last of the PCI write command retries fails due to a
Disconnect with(out) Data, the PLB Master Write Retry
Disconnect interrupt is asserted.
Target disconnect Completes
with data
PERR
Transaction completes and PLB Master Write PLB Master Write PERR interrupt asserted. If the burst
PERR interrupt asserted
write is still in progress, Sl_MErr is asserted with
Sl_wrDAck. The FIFO is flushed.
Latency timer
expiration
N/A because PCI32 core waits for one transfer
after timeout occurs
Automatically retried a parameterized number of times. If
the last of the PCI write command retries fails due to a
Latency Timer expiration, the PLB Master Burst Write
Retry Timeout interrupt is asserted. The PLB master must
reissue command per PCI spec if last termination was a
retry.
Target Abort
Assert PLB Master Write Target Abort
interrupt
Assert PLB Master Write Target Abort interrupt. If the
burst write is still in progress, Sl_MWrErr is asserted with
Sl_wrDAck.
Address
N/A
increments beyond
valid range
Stop PCI transaction. Assert PLB Write Slave BAR
Overrun interrupt.
PCI Initiator Initiates a Read Request of a PLB Slave
This section discusses the operation of a remote PCI initiator asserting both single and multiple read commands to
read data from a remote PLB slave. For these transactions, the PCI32 core is the PCI target.
Because all PLB address space must be memory space in the PCI sense, memory read, memory read multiple and
memory read line are the only read commands from a remote PCI initiator that the PLBV46 PCI Bridge responds to.
The I/O read command is ignored and the configuration read command is responded to by the PCI32 core, but has
limited impact on the PLBV46 PCI Bridge.
DS616 June 22, 2011
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Product Specification