DS616 Datasheet, PDF (4/60 Pages) Xilinx, Inc – LogiCORE IP PLBV46 PCI Full

LogiCORE IP PLBV46 PCI Full Bridge (v1.04.a)
Evaluation Version
The PLBV46 PCI Bridge is delivered with a hardware evaluation license. When programmed into a Xilinx device,
the core will function in hardware for about 8 hours at the typical frequency of operation. To use the PLBV46 PCI
Bridge without this timeout limitation, a full license must be purchased.
Functional Description
The PLBV46 PCI Bridge design is shown in Figure 1 and described in the following sections. As shown, PLB IPIF
PCI Bridge is comprised of three main modules:
• The PLB IPIF (Processor Local Bus Intellectual Property InterFace). It interfaces to the PLB bus.
• The IPIF v3.0 Bridge. It interfaces between the PLBV46 IPIF and the PCI32 core.
• The LogiCORE IP PCI32 core. It interfaces to the PCI bus.
X-Ref Target - Figure 1
PLB IPIF
IPIF/V3 Bridge
Xilinx
v3.0 PCI Core
Interrupt
Module
Bridge
Registers
Slave
Attachment
PCI2IPIF
FIFO
IPIF2PCI
FIFO
Master
Attachment
PCI2IPIF
FIFO
IPIF2PCI
FIFO
Master SM
Figure 1: PLBV46 PCI Full Bridge Block Diagram
DS616_01_040407
DS616 June 22, 2011
www.xilinx.com
4
Product Specification