DS616 Datasheet, PDF (51/60 Pages) Xilinx, Inc – LogiCORE IP PLBV46 PCI Full

LogiCORE IP PLBV46 PCI Full Bridge (v1.04.a)
Design Contraints
The PLBV46 PCI Bridge uses the PCI32 core that requires specific constraints to meet PCI specifications. UCF-files
with the constraints for the PCI32 core in many different packages are available from the LogiCORE IP Lounge. The
PCI32 core specific constraints can be included in the top-level UCF by the user.
The constraints are also implemented automatically in the EDK tool flow with any tool option that invokes bridge
synthesis. In this flow, TCL-scripts generate the UCF constraints and place them in a file in the PLBV46 PCI Bridge
directory of the project implementation directory. The UCF constraints are then included in the NGC file generated
in the EDK tool flow. The user can check the UCF in the implementation directory of the bridge directory to verify
that the constraints are included. As noted earlier, the user can include all constraints in the top-level UCF.
When the constraints are included in both the top-level UCF and the bridge NGC file (via the bridge directory
UCF), then the top-level UCF overrides any conflicting constraints in the bridge NGC file.
To remind the user that the following constraints must be included, PLATGEN generates the message:
The PLBV46 PCI Bridge design requires design constraints to guarantee performance. Please
refer to the PLBV46 IPIF/LogiCORE PCI bridge design data sheet for details.
Additional bridge specific constraints are required and an example UCF is provided in the EDK pcores library. To
remind the user that the additional bridge related constraints must be included in the top-level UCF, PLATGEN
generates the message:
An example UCF is available for this core and must be modified for use in the system. Please
refer to the EDK Getting Started guide for the location of this file.
The constraints that the PCI32 core require to meet PCI specifications are shown in the following constraints.
All I/O buffers must have IOB=TRUE
IOSTANDARD must explicitly list PCI33_3. Both BYPASS IOBDELAY=BOTH must be included for all PIC ports, as
shown in these examples.
NET "PCI_AD(*)" IOSTANDARD=PCI33_3;
NET "PCI_CBE(*)" IOSTANDARD=PCI33_3;
NET "PCI_PAR"
IOSTANDARD=PCI33_3;
NET "PCI_FRAME_N" IOSTANDARD=PCI33_3;
NET "PCI_TRDY_N" IOSTANDARD=PCI33_3;
NET "PCI_IRDY_N" IOSTANDARD=PCI33_3;
NET "PCI_STOP_N" IOSTANDARD=PCI33_3;
NET "PCI_DEVSEL_N" IOSTANDARD=PCI33_3;
NET "PCI_PERR_N" IOSTANDARD=PCI33_3;
NET "PCI_SERR_N" IOSTANDARD=PCI33_3;
#Include next 2 if routed to pins
NET "IDSEL" IOSTANDARD=PCI33_3;
NET "GNT_N" IOSTANDARD=PCI33_3;
NET "PCI_AD(*)" BYPASS;
NET "PCI_CBE(*)" BYPASS;
NET "PCI_PAR"
BYPASS;
NET "PCI_FRAME_N" BYPASS;
NET "PCI_TRDY_N" BYPASS;
NET "PCI_IRDY_N" BYPASS;
NET "PCI_STOP_N" BYPASS;
NET "PCI_DEVSEL_N" BYPASS;
NET "PCI_PERR_N" BYPASS;
NET "PCI_SERR_N" BYPASS;
#
DS616 June 22, 2011
www.xilinx.com
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Product Specification