DS616 Datasheet, PDF (29/60 Pages) Xilinx, Inc – LogiCORE IP PLBV46 PCI Full

LogiCORE IP PLBV46 PCI Full Bridge (v1.04.a)
Table 13: Bridge Interrupt Enable Register Bit Definitions (Bit assignment assumes 32-bit bus) (Cont’d)
Bit(s)
Name
Access
Reset
Value
Description
27 PLB Master
Write PERR
Read/Write
0x0 PLB Master Write PERR Enable- Enables this interrupt to be passed
to the interrupt controller.
• 0 - Not enabled.
• 1 - Enabled.
28 PLB Master
Write SERR
Read/Write
0x0 PLB Master Write SERR Enable- Enables this interrupt to be passed
to the interrupt controller.
• 0 - Not enabled.
• 1 - Enabled.
29 PLB Master
Read Target
Abort
Read/Write
0x0 PLB Master Read Target Abort Enable- Enables this interrupt to be
passed to the interrupt controller.
• 0 - Not enabled.
• 1 - Enabled.
30 PLB Master
Read PERR
Read/Write
0x0 PLB Master Read PERR Enable- Enables this interrupt to be passed
to the interrupt controller.
• 0 - Not enabled.
• 1 - Enabled.
31 PLB Master
Read SERR
Read/Write
0x0 PLB Master Read SERR Enable- Enables this interrupt to be passed
to the interrupt controller.
• 0 - Not enabled.
• 1 - Enabled.
PLBV46 PCI Bridge Reset Register Description
The IP Reset module is always instantiated in the PLBV46 PCI Bridge. Details on the IPIF Reset module can be
found in the Processor IP Reference Guide. The IP Reset module permits the software reset of the PLBV46 PCI Bridge,
independently of other modules in the system. However, the PCI32 core is not reset by the software reset and can
only be reset by the PCI bus RST_N signal. The MIR is not included.
Configuration Address Port Register Description
The Configuration Address Port Register exists only if the bridge is configured with PCI host bridge configuration
functionality, such as C_INCLUDE_PCI_CONFIG=1. This register is read/write with some bits hardwired as in
Table 14. Definition of this register is a subset of the PCI 2.2. All accesses to the register are 32-bit accesses. Data is
latched on a write in all 32-bits except where bits are hard-wired. A read yields all 32-bits. Reset clears all bits. Eight
and sixteen bit accesses are not supported, therefore, such accesses are not passed on as I/O accesses. Byte address
integrity is maintained from PCI little endian word format when writing/reading data to/from the Configuration
Address Port Register which is defined in big endian word format.
DS616 June 22, 2011
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