DS616 Datasheet, PDF (46/60 Pages) Xilinx, Inc – LogiCORE IP PLBV46 PCI Full

LogiCORE IP PLBV46 PCI Full Bridge (v1.04.a)
Table 25 shows the results of configuring the PCI32 core configuration header in the PLBV46 PCI Bridge by both
PLB-side configuration transactions and by remote PCI host bridge configuration transactions from the PCI-side.
This example assumes all PCI BARs are designated memory space which is the only allowed PCIBAR memory
type. The PLB-side configuration of the PCI32 core enables all functionality in the Command Status Register and
sets the latency timer to maximum count for most any data value written to the registers. This behavior is an artifact
of the v3.0 PCI32 core used in Spartan®-3 and Virtex-4 devices. However, the v4.0 PCI32 core used in the Virtex-5
device family DOES NOT exhibit this behavior.
Configuration Space Header
The PCI32 core used in the PLBV46 PCI Bridge can be configured with functionality to address a wide range of
applications.
Fields of the Configuration Space Header are Device ID, Vendor ID, Class Code, Rev ID, Subsystem ID, Subsystem
Vendor ID, Maximum Latency and Minimum Grant. The parameters for these fields are C_DEVICE_ID,
C_VENDOR_ID, C_CLASS_CODE, C_REV_ID, C_SUBSYSTEM_ID, C_SUBSYSTEM_VENDOR_ID, C_MAX_LAT,
C_MIN_GNT, respectively.
Listed in Table 25 are details on the remaining configuration registers that are fixed in value.
BIST, Line Size and Expansion ROM Base Address are not implemented in the PCI32 design.
Header Type is a fixed byte of all zeros in the PCI32 design.
Cardbus CIS Pointer is set to all zeros for the PCI32 implementation used in the PLBV46 PCI Bridge.
Capabilities Pointer is not enabled for the PCI32 implementation used in the PLBV46 PCI Bridge.
Interrupt Pin register is set to 0x01.
BAR3, BAR4 and BAR5 are not supported by the PCI32 Core. For these registers and un-implemented PCIBARs
(determined by C_PCIBAR_NUM), zeros are returned when read. Writes to the un-implemented configuration
space addresses have no effect.
Latency timer, BAR0, BAR1, and BAR2 are required to be set by the host bridge as necessary. The number of BARs
(0-3) is set by the parameter C_PCIBAR_NUM.
The User Configuration Space is enabled for the PCI32 implementation used in the PLBV46 PCI Bridge.
DS616 June 22, 2011
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