DS616 Datasheet, PDF (52/60 Pages) Xilinx, Inc – LogiCORE IP PLBV46 PCI Full

LogiCORE IP PLBV46 PCI Full Bridge (v1.04.a)
NET "*/RST_N"
NET "*/AD<*>"
NET "*/CBE<*>"
NET "*/REQ_N"
NET "*/GNT_N"
NET "*/PAR"
NET "*/IDSEL"
NET "*/FRAME_N"
NET "*/IRDY_N"
NET "*/TRDY_N"
NET "*/DEVSEL_N"
NET "*/STOP_N"
NET "*/PERR_N"
NET "*/SERR_N"
NET "*/PCI_INTA"
IOBDELAY = BOTH ;
IOBDELAY = BOTH ;
IOBDELAY = BOTH ;
IOBDELAY = BOTH ;
IOBDELAY = BOTH ;
IOBDELAY = BOTH ;
IOBDELAY = BOTH ;
IOBDELAY = BOTH ;
IOBDELAY = BOTH ;
IOBDELAY = BOTH ;
IOBDELAY = BOTH ;
IOBDELAY = BOTH ;
IOBDELAY = BOTH ;
IOBDELAY = BOTH ;
IOBDELAY = BOTH ;
TNM constraints must be defined as specified in the PCI32 Design Guide and PCI32 core UCFs. These parameters are
automatically set in the normal EDK tool flow, but can be included in the system top-level UCF. For alternative tool
flows, the settings are shown in the following Time Specs example. When the complete set of constraints is used, the
PCI clock must be a PAD input which is the required clock routing for all PCI32 core implementations. The EDK
flow checks if the PCI clock is a PAD input and if it is, then the OFFSET constraints shown in the following Time
Specs example are included in the bridge NGC file.
##########################################################################
# Time Specs
##########################################################################
#
# Important Note: The timespecs used in this section cover all possible
# paths. Depending on the design options, some of the timespecs might
# not contain any paths. Such timespecs are ignored by PAR and TRCE.
#
#
1) Clock to Output
=
11.000 ns
#
2) Setup
=
7.000 ns
#
3) Grant Setup
=
10.000 ns
#
4) Datapath Tristate
=
28.000 ns
#
5) Period
=
30.000 ns
#
# Note: Timespecs are derived from the PCI Bus Specification. Use of
# offset constraints allows the timing tools to automatically include
# the clock delay estimates. These constraints are for 33 MHz operation.
#
# The following timespecs are for setup.
#
TIMEGRP "PCI_PADS_D" OFFSET=IN 7.000 VALID 7.000 BEFORE "PCI_CLK" TIMEGRP "ALL_FFS" ;
TIMEGRP "PCI_PADS_B" OFFSET=IN 7.000 VALID 7.000 BEFORE "PCI_CLK" TIMEGRP "ALL_FFS" ;
TIMEGRP "PCI_PADS_P" OFFSET=IN 7.000 VALID 7.000 BEFORE "PCI_CLK" TIMEGRP "ALL_FFS" ;
TIMEGRP "PCI_PADS_C" OFFSET=IN 7.000 VALID 7.000 BEFORE "PCI_CLK" TIMEGRP "ALL_FFS" ;
#
# The following timespecs are for clock to out where stepping is not used.
#
TIMEGRP "PCI_PADS_D" OFFSET=OUT 11.000 AFTER "PCI_CLK" TIMEGRP "FAST_FFS" ;
TIMEGRP "PCI_PADS_B" OFFSET=OUT 11.000 AFTER "PCI_CLK" TIMEGRP "FAST_FFS" ;
TIMEGRP "PCI_PADS_P" OFFSET=OUT 11.000 AFTER "PCI_CLK" TIMEGRP "FAST_FFS" ;
TIMEGRP "PCI_PADS_C" OFFSET=OUT 11.000 AFTER "PCI_CLK" TIMEGRP "ALL_FFS" ;
DS616 June 22, 2011
www.xilinx.com
52
Product Specification