DS616 Datasheet, PDF (53/60 Pages) Xilinx, Inc – LogiCORE IP PLBV46 PCI Full

LogiCORE IP PLBV46 PCI Full Bridge (v1.04.a)
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# The following timespecs are for clock to out where stepping is used.
#
TIMEGRP "PCI_PADS_D" OFFSET=OUT 28.000 AFTER "PCI_CLK" TIMEGRP "SLOW_FFS" ;
TIMEGRP "PCI_PADS_B" OFFSET=OUT 28.000 AFTER "PCI_CLK" TIMEGRP "SLOW_FFS" ;
TIMEGRP "PCI_PADS_P" OFFSET=OUT 28.000 AFTER "PCI_CLK" TIMEGRP "SLOW_FFS" ;
Target Technology
The intended target technology is for the Spartan-3, Spartan-6, Virtex-4, and Virtex-5 FPGAs.
Virtex-4 and Virtex-5 FPGA Support
To meet PCI specification setup and hold times with the Virtex-4 and Virtex-5 architectures, it is necessary to insert
an IDELAY primitive between the pad and I/O buffer of most PCI signals and to include additional constraints in
the UCF. When IDELAY primitives are used in the mode required by the PCI32 core, IDELAYCTRL (idelay
controllers) are required. Also required is a 200 MHz reference clock supplied by the user which is used by both
IDELAY and IDELAYCTRL primitives. These primitives are only required for Virtex-4 and Virtex-5 architectures.
The additional constraints are discussed after the discussion of primitives specific to Virtex-4 and Virtex-5 devices.
The 200 MHz clock is input to port RCLK and must be driven by a global buffer. If the architecture is not off the
Virtex-4 or Virtex-5 devices, the port does not connect to anything in the plbv46_pci bridge, and it might be omitted
from the MHS-file. This allows upgrading to v1.02.a from v1.01.a without changing ports. Recall that v1.01.a does
not support the Virtex-4 architecture. It is required that the 200 MHz clock be stable when PLB_RST is asserted to
the PLBV46 PCI Bridge. An unstable clock can result failure of PLBV46 PCI Bridge operation. The clock source can
be an external source or generated with a DCM in the FPGA. Application Notes and Implementation Guides for the
PCI32 core, as well as reference designs using the PLBV46 PCI Bridge, present options for generating the 200 MHz
clock.
IDELAY primitives are instantiated automatically by the bridge when the C_FAMILY parameter is set to the
Virtex-4 or Virtex-5 architecture. The EDK tools automatically set this parameter and it cannot be changed by the
user. There is a special case to consider for instantiation of IDELAY primitives. Port GNT_N requires the IDELAY
primitive only if the port is connected to a package pin. If GNT_N is connected to an internal signal (an FPGA
internal arbiter such as pci_arbiter_v1_00_a) or connected to ground, then an IDELAY primitive is not needed. EDK
tools have the system level information to determine if GNT_N is connected to a pad or has an internal connection.
This accomplished with a TCL-script in the PLBV46 PCI Bridge pcore library that is called by the EDK tools.
EDK tools automatically sets the parameter C_INCLUDE_GNT_DELAY which controls if an IDELAY primitive is
included in the GNT_N signal path. C_INCLUDE_GNT_DELAY defaults to exclude the IDELAY primitive and
must be set by the user if the core is used outside EDK tools with GNT_N connected to a pin.
IDELAYCTRL primitives are not as automatic in the build procedure. It is required that the user instantiate the
number of IDELAYCTRL primitive needed for their design and to provide LOC contraints for each IDELAYCTRL.
This is required for EDK 8.1 tools because when instantiating only one IDELAYCTRl without LOC constraints, the
tools will replicate the primitive throughout the design. Replicating the primitive has the undesirable results of
higher power consumption, higher power consumption, utilization of more global clock resources, and greater use
of routing resources. To prevent these undesirable results, a procedure is described in the next paragraph for
instantiating the IDELAYCTRLs. See the Virtex-4 FPGA User Guide discussion of IDELAYCTRL usage and design
guidance for more details on IDELAYCTRL and usage. Tools beyond ISE® software 7.1 might handle IDELAYCTRL
instantiation differently.
DS616 June 22, 2011
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Product Specification