DS616 Datasheet, PDF (60/60 Pages) Xilinx, Inc – LogiCORE IP PLBV46 PCI Full

LogiCORE IP PLBV46 PCI Full Bridge (v1.04.a)
Table 31: List of Acronyms (Cont’d)
Acronym
Description
MHz
MPLB
MRL
MWI
NGC
PCI
PCIBAR
PERR
PLB
RAM
SERR
SPLB
SRAM
TCL
UCF
XPS
XST
Mega Hertz
Master Processor Local Bus
Memory Read Line
Memory Write Invalidate
Native Generic Circuit
Peripheral Component Interconnect
Peripheral Component Interconnect Base Address Register
Parity Error
Processor Local Bus
Random Access Memory
System Error
Slave Processor Local Bus
Static RAM
Tool Command Language
User Constraints File
Xilinx Platform Studio (part of the EDK software)
Xilinx Synthesis Technology
Revision History
Date
Version Revision
12/11/07 1.0
Initial Xilinx Release
1/10/08
1.1
Changed erroneous OPB reference to PLB in Features section
4/11/08
1.2
Added text re: pull-up resistors to PCI Core Requirements, cross clock constraints to Design
Constraints
12/10/08 1.3
Updated to core version v1.03.a and 10.1 design tools.
6/22/11
1.4
Updated to core version v1.04.a and 13.2 design tools.
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DS616 June 22, 2011
www.xilinx.com
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Product Specification