DS616 Datasheet, PDF (16/60 Pages) Xilinx, Inc – LogiCORE IP PLBV46 PCI Full

LogiCORE IP PLBV46 PCI Full Bridge (v1.04.a)
Table 2: PLBV46 PCI Bridge I/O Signals (Cont’d)
Port
Signal Name
Interface
I/O
Description
PCI Arbitration Signals
P88 REQ_N
PCI Bus
O Indicates to the arbiter that the PCI32 initiator requests
access to the bus
P89 GNT_N
PCI Bus
I Indicates that the arbiter has granted the bus to the PCI32
initiator
PCI System Signals
P90 RST_N
PCI Bus
I PCI bus reset signal is used to bring PCI-specific registers,
sequences, and signals to a consistent state
P91 PCLK
PCI Bus
I PCI bus clock signal
PCI Bus Internal Arbiter Signals
P92 INTR_A_int
Internal
O INT_A available to internal arbiter
P93 REQ_N_toArb
Internal
O Input from PCI Bus REQ_N available at top-level as output
from bridge
P94 FRAME_I
Internal
O Input from PCI Bus FRAME_N availalble at top-level as
output from bridge
P95 IRDY_I
Internal
O Input from PCI Bus IRDY_N availalble at top-level as output
from bridge
User Asserted PCI Interrupt Signal
P96 Bus2PCI_INTR
Internal
I Active high signal to asynchronously assert INTR_A.
Inverted signal drives INTR_N user application input of PCI
core. See PCI core documents for details on INTR_N
functionality.
Virtex-4 or Virtex-5 FPGA Only, IDELAY Clock
P97 RCLK
Internal
I 200 MHz clock input to IDELAY elements of Virtex-4 and
Virtex-5 FPGA buffers. Ignored if not Virtex-4 or Virtex-5
architectures.
PCI Bus Monitoring Debug Vector Signal
P98 PCI_monitor(0:47)
Note:
Internal
O Output vector to monitor PCI Bus.
1. This function and timing of this signal are defined in the IBM 128-Bit Processor Local Bus Architecture Specification Version 4.6.
The REQ_N_toArb facilitates an interface to an internal (in the FPGA) pci arbiter. The PCI input buffer for GNT_N
is removed. This allows an internal connection to GNT_N when using an internal arbiter. When an external arbiter
is used, GNT_N_fromArb is not needed.
REQ_N is a 3-stated I/O. The REQ_N_toArb port is available to maintain a PCI core-like interface. The
REQ_N_toArb port allows the use of the same port list for PCI bus interface and the UCF for the PCI32 core is the
standard file.
The PCI32 core requires that GNT_N be asserted for two clock cycles to initiate a transaction upon receiving grants.
Bus2PCI_INTR is an active High signal. It allows asynchronous assertion of INTR_A on the PCI bus. The signal is
driven by user supplied circuitry, such as a PLB GPIO IP core. If it is not connected in the mhs-file, then EDK tools
will tie the signal Low. The signal is inverted in the PLBV46 PCI Bridge and AND’d with the bridge interrupt signal
(active Low) to drive the INTR_N input of the PCI32 core. This signal then asynchronously drives INTR_A on the
PCI bus. See the PCI32 core specifications on INTR_A behavior relative to PCI input INTR_N.
DS616 June 22, 2011
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Product Specification