DS616 Datasheet, PDF (10/60 Pages) Xilinx, Inc – LogiCORE IP PLBV46 PCI Full

LogiCORE IP PLBV46 PCI Full Bridge (v1.04.a)
Table 1: PLBV46 PCI Bridge Interface Design Parameters (Cont’d)
Generic
G35
G36
Feature / Description Parameter Name
Allowable Values
Both PCI2IPIF FIFO
address bus widths. Usable
depth is
2^C_PCI2IPIF_FIFO_
ABUS_WIDTH - 3
C_PCI2IPIF_
FIFO_ABUS_
WIDTH
7-11⁽³⁾
Both IPIF2PCI FIFO
address bus widths. Usable
depth is
2^C_IPIF2PCI_FIFO_
ABUS_WIDTH - 3
C_IPIF2PCI_
FIFO_ABUS_
WIDTH
7-11⁽³⁾
Default Value VHDL Type
9
integer
9
integer
G37 Include explicit instantiation C_INCLUDE_
of INTR_A io-buffer (must INTR_A_BUF
be 1 to include io-buffer)
0 = not included
1 = included
1
integer
G38 Include explicit instantiation C_INCLUDE_
of REQ_N io-buffer (must REQ_N_BUF
be 1 to include io-buffer)
0 = not included
1 = included
1
integer
G39 This parameter is no longer C_TRIG_IPIF_
2 to the lesser of 24 or the
8
active. However, if it is set WRBURST_
PCI2IPIF FIFO DEPTH-3.
by the user, it must still have OCC_LEVEL
PCI2IPIF FIFO DEPTH
an allowable value.
given by
2^C_PCI2IPIF_FIFO_ABUS
_WIDTH
integer
G40 IPIF2PCI FIFO occupancy C_TRIG_PCI_
2 to the lesser of 24 or the
8
level that starts data
DATA_XFER_
IPIF2PCI FIFO DEPTH-3.
transfer (Both as initiator OCC_LEVEL
IPIF2PCI FIFO DEPH given
and target on PCI) to PCI
by 2^C_IPIF2PCI_FIFO_
agent with multiple data
ABUS_WIDTH
phases per transfer (must
meet 16 PCI period
maximum).
integer
G41 Number of PCI retry
C_NUM_PCI_RET Any integer
attempts in IPIF
RIES_IN_
posted-write operations
WRITES
3
integer
G42 Number of PCI clock
C_NUM_PCI_PRD Any integer
periods between retries in S_BETWN_
posted- write operations RETRIES_IN_
WRITES
G43 Device base address
C_BASE
ADDR
Valid PLB address ^{(1), (2)}
G44 Device absolute high
address
C_HIGHADDR
Valid PLB address ^{(1), (2)}
6
integer
0xFFFFFFFF
0x00000000
std_logic_
vector
std_logic_
vector
G45 Include the registers for
C_INCLUDE_
1 = include
high-order bits to be
substituted in translation
BAROFFSET_RE _{0 = exclude}
G
0
integer
G46 Include the register for local C_INCLUDE_DEV 1 = include
bridge device number when NUM_REG
configuration functionality
0 = exclude
(C_INCLUDE_PCI_CONFI
G =1) is included
0
integer
G47 Length of PCI Initiated burst C_PCI_INIT_RD_ 2-128
reads (in words)
BURST_LENGTH
16
integer
DS616 June 22, 2011
www.xilinx.com
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Product Specification