DS616 Datasheet, PDF (42/60 Pages) Xilinx, Inc – LogiCORE IP PLBV46 PCI Full

LogiCORE IP PLBV46 PCI Full Bridge (v1.04.a)
The PLBV46 PCI Bridge translates a PCI memory read multiple command to a PLB burst read. A PCI memory read
command that is asserted with multiple data phases requested, such as when FRAME# and IRDY# are asserted on
the same clock, is also translated to a PLB burst read. A PCI memory read command that is asserted with a single
data phases requested is translated to a PLB single read, such as when FRAME# is deasserted prior to IRDY# being
asserted. Table 20 shows translations of PCI commands to PLB transactions.
For PCI memory read commands that are translated to a PLB single read, the address presented on the PCI is
translated to the PLB address space by high-order bit substitution with the 2 LSBs set as defined by the byte enable
vector for the first data phase. The LSBs are set to the lowest address of the byte lane asserted in the byte enable
vector as required by the Xilinx PLB specification. Byte enables from the PCI bus are passed correctly to the PLB in
single PLB read transactions. For PCI commands that are translated to a PLB burst read, the address presented on
the PLB is word aligned.
Every PCI command that translates to a burst read operation is performed with the full 32 bits on the PLB
independent of the byte enable specified by the PCI initiator. The byte enable bits asserted by the PCI initiator in
memory read multiple operations of a PLB slave are ignored, and all bytes are read during the PLB burst read
operation per PLB protocol. Hence, dynamic byte enable is not supported by PCI initiator burst read from PLB
slaves. The system designer must ensure that a burst read with all byte enables asserted is not destructive.
The user must ensure that corrupting the fidelity of the PCI read command with arbitrary byte enables asserted by
translating to a PLB burst with all byte enable asserted is not destructive.
Furthermore, it is the responsibility of the PCI initiator to properly read data from non-prefetchable PLB slaves. For
example, it must perform single transaction reads of non-prefetchable PLB slaves to avoid destructive read
operations of a PLB slave. However, some protection is provided in the hardware as described in a later subsection.
When the PLBV46 PCI Bridge decodes a PCI read command that is for a remote PLB Slave, the transfer is retried on
the PCI bus until the requested data has been prefetched from the remote PLB Slave. This is true for both single and
burst transactions. Only one PCI initiator read of a PLB slave is supported at a time. After this transaction is
successfully completed, a subsequent PCI read with the same PCI command and address then completes on the PCI
bus.
A Discard Timer is used to determine how long the PLBV46 PCI Bridge should wait for a subsequent PCI read with
the same PCI command and address before discarding the prefetched data in the FIFO.
Data throughput can be very high with burst read transactions. The PCI commands that translate to burst read
operations will burst read with a length determined by either a parameterized number or up to the range limit of
the PCI BAR, whichever is less. The prefetch read does not read beyond the high-address defined by the PCI BAR
length parameter. After the remote PCI initiator terminates the read transaction, the FIFO is flushed of prefetched
data that has not been read by the remote PCI initiator.
Abnormal Terminations
• If an address parity error is detected, the PCI32 core will either claim the transaction and issue a Target Abort,
or will not claim the transaction and a Master Abort will occur (see PCI32 core documentation). When a Target
Abort is issued, the PCI32 core asserts SERR_N, if enabled.
• If SERR_N is asserted by a remote agent in a data phase on either a single or a burst transfer, it is left to the PCI
initiator to report the error and initiate any recovery effort that may be needed. The PLBV46 PCI Bridge
disconnects with data as soon as possible and any data left is the internal FIFOs are discarded.
• If, on either a single or a burst transfer, a PERR error is detected during a data phase, the PLBV46 PCI Bridge
does nothing. Whether the PCI initiator continues or not is initiator dependent.
DS616 June 22, 2011
www.xilinx.com
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Product Specification