DS616 Datasheet, PDF (34/60 Pages) Xilinx, Inc – LogiCORE IP PLBV46 PCI Full

LogiCORE IP PLBV46 PCI Full Bridge (v1.04.a)
The PCI transactions that are supported is limited to a subset of all PCI transactions because some features on the
PCI are not supported on the PLB. Specifically, dynamic byte enable during multiple data phase transfers is not
supported in burst transactions on the PLB. The PLB supports only full words in burst read and write transactions.
It is the user’s responsibility to ensure that all byte enables are asserted for remote PCI initiator transactions with
multiple data phases.
Table 19: Translation Table for PLB transactions to PCI commands
Remote PLB Master
Transaction
Single Read (<=4 bytes)
Read Burst transfer word
Sequential Read, 4, 8 and
16-word cacheline read ⁽¹⁾
Single Write (<=4 bytes)
Write Burst transfer word
PCI I/O Space Prefetchable
or Non-prefetchable
I/O Read
I/O Read
I/O Read
I/O Write
I/O Write
Sequential fill, 4, 8 and 16-word
cacheline write ⁽²⁾
Notes:
I/O Write
PCI Memory Space
Prefetchable
Memory Read
Memory Read Multiple
Memory Read Multiple
Memory Write
Memory Write (multiple data
phase)
Memory Write (multiple data
phase)
PCI Memory Space
Non-prefetchable
Not Supported
Not Supported
Not Supported
Not Supported
Not Supported
Not Supported
1. The data is returned sequentially, starting at the first word of the line. This is independent of the target word presented.
2. On write, the 405 always sources the first word, for example, sequential fill, on the line.
Table 20: Translation Table for PCI commands to PLB transactions
PCI Initiator Command
I/O Read
I/O Write
Memory Read
(single data phase)
Memory Read
(multiple data phase)
Memory Read Multiple
Memory Read Line
Memory Write
(single data phase)
Memory Write ²
(multiple data phase)
Memory Write Invalidate
Notes:
PLB Memory Prefetchable
Not Supported
Not Supported
PLB Single Read
PLB Burst Read with all BE asserted ⁽¹⁾
PLB Burst Read with all BE asserted ⁽¹⁾
PLB Single Read
PLB Single Write
PLB Burst Write of length defined by
available data in FIFO ⁽²⁾
PLB Burst Write
PLB Memory Non-prefetchable
Not Supported
Not Supported
Not Supported
Not Supported
Not Supported
Not Supported
Not Supported
Not Supported
Not Supported
1. The PLB does not support dynamic byte enable (BE) in burst read transactions so when Memory Read Multiple is translated
to a PLB burst read, all BE are asserted during the PLB read operation.
2. The PLB does not support dynamic byte enable (BE) in burst write transactions so when Memory Write Multiple is translated
to a PLB burst write, all BE are asserted during the PLB write operation.
DS616 June 22, 2011
www.xilinx.com
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Product Specification