DS616 Datasheet, PDF (31/60 Pages) Xilinx, Inc – LogiCORE IP PLBV46 PCI Full

LogiCORE IP PLBV46 PCI Full Bridge (v1.04.a)
IPIFBAR2PCIBAR_N High-Order Bits Register Description
When configured to include these registers, such as C_INCLUDE_BAROFFSET_REG=1, the values in the registers are
used to translate addresses on the PLB bus to the PCI. The register values are used instead of the corresponding
parameter C_IPIFBAR2PCIBAR_N for translation by high-order bit substitution. The parameters
C_IPIFBAR2PCIBAR_N have no effect on the bridge operation if the registers for address translation are included.
The number of registers present is given by the number of IPIF BAR configured in the IPIF (C_IPIFBAR_NUM). The
actual width of the Nth register is given by the number of high-order bits that define the complete address range
corresponding to the Nth IPIF BAR. When the register is read, 32-bits are returned with the low-order bits
hard-wired to zero.
The IPIFBAR2PCIBAR_N registers are included in the bridge via the parameter C_INCLUDE_BAROFFSET_REG.
These read/write registers allow dynamic, run-time changes of the high-order bits for the substitution in the
translation of an address from the PLB bus to the PCI bus. Low-order bits pass directly from the PLB bus to the PCI
bus. When the register is read, 32-bits are read with the low-order bits set to zero. Table 17 shows the data format.
The programmability of these registers allows PLB address transactions to access any target on the PCI bus which
has been arbitrarily assigned a PCI BAR by a remote or local Host Bridge. Dynamic, run-time changes in the
high-order bits for address translation of PLBV46 PCI Bridge PCI BAR range translation to PLB slaves is not needed
because the PLB slave addresses are defined at build time.
Including these registers makes the parameters, C_IPIFBAR2PCIBAR_N, irrelevant because the value in the Nth
programmable register replaces the values of the corresponding parameter, C_IPIFBAR2PCIBAR_N, in translating
the PLB address to the PCI bus. When the registers are included, the parameters, C_IPIFBAR2PCIBAR_N, for N=0
to C_IPIFBAR_NUM-1, have no effect.
Table 17: IPIFBAR2PCIBAR_N High-Order Bits (Bit assignment assumes 32-bit bus)
Bit(s)
Name
Access
Reset
Value
Description
0-M
D0 - DM
Read/Write
0x0 M+1 high-order bits that are substituted in address translation
from Nth IPIFBAR access to PCI address space
M+1-31
DM+1 - D31
Read Only
0x0 Low-order bits set to zero
The following example shows how the IPIFBAR2PCIBAR_N registers assignments define translation of PLB
addresses within the range of a given IPIFBAR to PCI address space.
Setting C_INCLUDE_BAROFFSET_REG=1 includes high-order bit registers for all IPIFBARs defined by
C_IPIFBAR_NUM.
In this example where C_IPIFBAR_NUM=4, the following assignments for each range are made.
C_IPIFBAR_0=0x12340000
C_IPIF_HIGHADDR_0=0x1234FFFF
C_IPIFBAR2PCIBAR_0=Don’t care
C_IPIF_SPACETYPE_0=1
C_IPIFBAR_1=0xABCDE000
C_IPIF_HIGHADDR_1=0xABCDFFFF
C_IPIFBAR2PCIBAR_1=Don’t care
C_IPIF_SPACETYPE_1=0
DS616 June 22, 2011
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Product Specification