DS616 Datasheet, PDF (49/60 Pages) Xilinx, Inc – LogiCORE IP PLBV46 PCI Full

LogiCORE IP PLBV46 PCI Full Bridge (v1.04.a)
Multiple PLBV46 PCI Bridges can be instantiated on a given PLB. Each bridge has a unique base address with fixed
offset to corresponding unique set of configuration registers. The unique set of configuration registers are used to
perform configuration accesses on the unique primary PCI bus and its’ subordinate buses. Device numbers are
independent for each PLBV46 PCI Bridge instantiated, but bus numbering must be monotonically increasing for all
primary buses and their subordinate buses.
Abnormal Terminations
Responses to abnormal terminations of Configuration Reads and Writes follow closely to single reads and writes by
a remote PLB master from or to a remote PCI target. Details of each transaction can be reviewed in the previous
sections; however, some differences exist. Shown in Table 27 is a table summary of responses to abnormal
terminations during configuration transactions. The differences as compared to PLB master read and writes to
remote targets are shown.
Table 27: Response of PLB Master/v3.0 Initiator Configuration Transactions with abnormal condition on
PCI bus
Abnormal Condition
Configuration Read
Configuration Write
SERR (including address phase parity Return all ones and set PLB
error)
Master Read SERR interrupt
PLBV46 PCI Bridge Master abort (no All 1s are returned
PCI target response)
Target disconnect without data (PCI Automatically retried until the
Retry)
transfer completes
PLB Master Write SERR interrupt asserted
PLB Master Abort Write interrupt asserted
Automatically retried a parameterized number of
times. If the last of the PCI write command retries
fail due to a PCI retry, the PLB Master Burst Write
Retry interrupt is asserted. The PLB master must
reissue command per PCI specification, if last
termination was a retry.
Target disconnect with data
PERR
Latency timer expiration
Latency timer register must be set to
non-zero value for accessing remote
devices.
Completes
Data is transferred and PLB
Master Read PERR interrupt is
asserted
N/A because PCI32 core waits
for one transfer after timeout
occurs when latency timer is
non-zero
Completes
Transaction completes and PLB Master Write
PERR interrupt asserted
N/A because PCI32 core waits for one transfer after
timeout occurs when latency timer is non-zero
Target Abort
Set PLB Master Read Target
Abort interrupt and terminate
PLB transaction with Slv_MErr
assertion
Assert PLB Master Write Target Abort interrupt.
DS616 June 22, 2011
www.xilinx.com
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Product Specification