DS616 Datasheet, PDF (37/60 Pages) Xilinx, Inc – LogiCORE IP PLBV46 PCI Full

LogiCORE IP PLBV46 PCI Full Bridge (v1.04.a)
Abnormal Terminations
In the context of the PLBV46 PCI Bridge, cacheline transactions are special cases of a burst. Abnormal terminations
during a cacheline read operation have the same response as a burst read transaction.
• If a parity error occurs during the address phase of the prefetch, the PLBV46 PCI Bridge asserts the PLB Master
Read SERR interrupt. If the remote PCI target follows the response recommended by the PCI specification to
not claim the transactions, the PLBV46 PCI Bridge terminates the transaction with a master abort. If the target
does not follow PCI specification recommendation and transfers data, the received data is discarded and not
available to the remote PLB Master. Sl_MRdErr is asserted at the first opportunity.
• If a SERR occurs during a valid data phase on a single transfer, the PLBV46 PCI Bridge asserts the PLB Master
Read SERR interrupt. The received data is discarded and not available to the remote PLB Master. Sl_MRdErr is
asserted at the first opportunity.
• If a SERR occurs during a valid data phase on a burst transfer, the PLBV46 PCI Bridge asserts the IPIF Master
Read SERR interrupt. SERR error on data phase could occur on the first PCI transaction or on a subsequent
transaction due to an abnormal disconnect that allowed automatic reissue of the PCI read command. The
received data is discarded and not available to the remote PLB Master. Sl_MRdErr is asserted at the first
opportunity.
• If the PLBV46 PCI Bridge performs a master abort due to no response from a target, the prefetch is abandoned.
Sl_MRdErr is asserted at the first opportunity.
• If on either a single transfer or the first data phase of a burst transfer, a PCI retry from the PCI target occurs, the
PLBV46 PCI Bridge immediately retries the read request and continue retrying the request until the transfer
completes.
• If during a single transfer the target disconnects with data, the transfer will be completed.
• If on a single transfer, a PERR error is detected, data is transferred and the PLB Master Read PERR interrupt is
asserted.
• If the target disconnects on a burst transfer, either with or without data, the PCI32 core terminates the PCI
transaction. Another PCI transaction is attempted as long as the encoded length specified in the PLB
fixed-length burst transfer has not been prefetched.
• If a PERR error is detected on a burst transfer, the PLBV46 PCI Bridge aborts the PCI transaction. Any received
data is discarded and not available to the remote PLB Master. The PLB Master Read PERR interrupt is asserted.
Sl_MRdErr is asserted at the first opportunity.
• If the initiator latency timer expires on a burst transfer, the PLBV46 PCI Bridge terminates the PCI transaction.
Another PCI transaction is attempted as long as the encoded length specified in the PLB fixed-length burst
transfer has not been prefetched.
• If a target abort occurs, the PLB Target Abort Master Read interrupt is asserted. Any received data is discarded
and not available to the remote PLB Master. Sl_MRdErr is asserted at the first opportunity. Recall that a target
abort indicates that the target cannot proceed with subsequent transactions; this is expected to be a major
failure most likely requiring a reset.
• If a PLB read request indicates a burst length that extends beyond the valid range of the IPIF BAR, as defined
by the C_IPIF_HIGHADDR_X parameter, the PLB Read Slave BAR Overrun interrupt is asserted. The PLBV46
PCI Bridge does not initiate a read on the PCI bus and responds to the PLB Master with Sl_MRdErr asserted
with Sl_rdDAck.
DS616 June 22, 2011
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Product Specification