W79E217A Datasheet, PDF (94/207 Pages) Winbond – 8-bit Microcontroller

Preliminary W79E217A Data Sheet
12. PROGRAMMABLE TIMERS/COUNTERS
The W79E217 has three 16-bit programmable timer/counters.
12.1 Timer/Counters 0 & 1
TM0 and TM1 are 16-bit Timer/Counters, and there are nearly identical. Each of these Timer/Counters
has two 8 bit registers which form the 16 bits counting register. For Timer/Counter 0, it consists of
TH0, the upper 8 bits register, and TL0, the lower 8 bit register. Similarly Timer/Counter 1 has two 8
bits registers; TH1 and TL1. The two timers can be configured to operate either as timers, counting
machine cycles or as counters counting external inputs.
When configured as a "Timer", the timer counts clock cycles. In "Counter" mode, the register is
incremented on the falling edge of the corresponding external input pins, T0 for Timer 0 and T1 for
Timer 1. The T0 and T1 inputs are sampled in every machine cycle at C4. If the sampled value is high
in one machine cycle and low in the next, then a valid high to low transition on the pin is recognized
and the count register is incremented. Since it takes two machine cycles to recognize a negative
transition on the pin, therefore the maximum counting rate is 1/8 of the master clock frequency. In both
"Timer" and "Counter" mode, the count register is updated at C3. Therefore, in the "Timer" mode, the
recognized negative transition on pin T0 and T1 can cause the count register value to be updated only
in the machine cycle following the one in which the negative edge was detected.
The "Timer" or "Counter" function is selected by the " C/T " bit in the TMOD Special Function Register.
Each Timer/Counter has one selection bit for its own; bit 2 of TMOD selects the function for
Timer/Counter 0 and bit 6 of TMOD selects the function for Timer/Counter 1. In addition each
Timer/Counter can be set to operate in any one of four possible modes. The mode selection is done
by bits M0 and M1 in the TMOD SFR.
12.1.1 Time-Base Selection
The W79E217 can operate like the standard 8051/52 family, counting at the rate of 1/12 of the clock
speed, or in turbo mode, counting at the rate of 1/4 clock speed. The speed is controlled by the T0M
and T1M bits in CKCON, and the default value is zero, which uses the standard 8051/52 speed.
12.1.2 Mode 0
In Mode 0, the timer/counter is a 13-bit counter. The 13-bit counter consists of THx (8 MSB) and the
five lower bits of TLx (5 LSB). The upper three bits of TLx are ignored. The timer/counter is enabled
when TRx is set and either GATE is 0 or INTx is 1. When C/T is 0, the timer/counter counts clock
cycles; when C/T is 1, it counts falling edges on T0 (P3.4 for Timer 0) or T1 (P3.5 for Timer 1). For
clock cycles, the time base may be 1/12 or 1/4 clock speed, and the falling edge of the clock
increments the counter. When the 13-bit value moves from 1FFFh to 0000h, the timer overflow flag
TFx is set, and an interrupt occurs if enabled. This is illustrated in next figure below.
- 94 -
Publication Release Date: December 14, 2007
Revision A3.0