W79E217A Datasheet, PDF (93/207 Pages) Winbond – 8-bit Microcontroller

Preliminary W79E217A Data Sheet
11.2.1 Response Time
The response time for each interrupt source depends on several factors like nature of the interrupt and
the instruction under progress. In the case of external interrupt INT0 to INT5, they are sampled at C3
of every machine cycle and then their corresponding interrupt flags IE0 and IE1 will be set or reset.
Similarly, the Serial port flags RI/RI_1 and TI/TI_1 are set in C4 of last machine cycle. The Timer 0
and 1 overflow flags are set at C3 of the machine cycle in which overflow has occurred. These flag
values are polled only in the next machine cycle. If a request is active and all three conditions are met,
then the hardware generated LCALL is executed. This call itself takes four machine cycles to be
completed. Thus there is a minimum time of five machine cycles between the interrupt flag being set
and the interrupt service routine being executed.
A longer response time should be anticipated if any of the three conditions are not met. If a higher or
equal priority is being serviced, then the interrupt latency time obviously depends on the nature of the
service routine currently being executed. If the polling cycle is not the last machine cycle of the
instruction being executed, then an additional delay is introduced. The maximum response time (if no
other interrupt is in service) occurs if the device is performing a write to IE, IP, IPH, EIE, EIP, EIPH,
EIE1, EIP1 or EIP1H and then executes a MUL or DIV instruction. From the time an interrupt source is
activated, the longest reaction time is 12 machine cycles. This includes 1 machine cycle to detect the
interrupt, 2 machine cycles to complete the IE, IP, IPH, EIE, EIP, EIPH, EIE1, EIP1 or EIP1H access,
5 machine cycles to complete the MUL or DIV instruction and 4 machine cycles to complete the
hardware LCALL to the interrupt vector location.
Thus in a single-interrupt system the interrupt response time will always be more than 5 machine
cycles and not more than 12 machine cycles. The maximum latency of 12 machine cycle is 48 clock
cycles. Note that in the standard 8051 the maximum latency is 8 machine cycles which equals 96
machine cycles. This is a 50% reduction in terms of clock periods.
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Publication Release Date: December 14, 2007
Revision A3.0