W79E217A Datasheet, PDF (140/207 Pages) Winbond – 8-bit Microcontroller

Preliminary W79E217A Data Sheet
The serial port receives data when REN is 1 and RI is zero. The shift clock (TxD) is activated, and the
serial port latches data on the rising edge of the shift clock. The external device should, therefore,
present data on the falling edge of the shift clock. This process continues until all eight bits have been
received. The RI flag is set in C1 following the last rising edge of the shift clock, which stops reception
until RI is cleared by the software.
16.2 Mode 1
In Mode 1, full-duplex asynchronous communication is used. Frames consist of ten bits transmitted on
TXD and received on RXD. The ten bits consist of a start bit (0), eight data bits (LSB first), and a stop
bit (1). When receiving, the stop bit goes into RB8 in SCON. The baud rate in this mode is 1/16 or 1/32
of the Timer 1 overflow, and since Timer 1 can be set to a wide range of values, a wide variation of
baud rates is possible.
Transmission begins with a write to SBUF but is synchronized with the divide-by-16 counter, not the
write to SBUF. The start bit is put on TxD at C1 following the first roll-over of the divide-by-16 counter,
and the next bit is placed at C1 following the next rollover. After all eight bits are transmitted, the stop
bit is transmitted. The TI flag is set in the next C1 state, or the tenth rollover of the divide-by-16
counter after the write to SBUF.
Reception is enabled when REN is high, and the serial port starts receiving data when it detects a
falling edge on RxD. The falling-edge detector monitors the RxD line at 16 times the selected baud
rate. When a falling edge is detected, the divide-by-16 counter is reset to align the bit boundaries with
the rollovers of the counter. The 16 states of the counter divide the bit time into 16 slices. Bit detection
is done on a best-of-three basis using samples at the 8th, 9th and 10th counter states. If the first bit
after the falling edge is not 0, the start bit is invalid, reception is aborted immediately, and the serial
port resumes looking for a falling edge on RxD. If a valid start bit is detected, the rest of the bits are
shifted into SBUF. After shifting in eight data bits, the stop bit is received. Then, if;
1. RI is 0, and
2. SM2 is 0 or the received stop bit is 1,
the stop bit goes into RB8, the eight data bits go into SBUF, and RI is set. Otherwise, the received
frame is lost. In the middle of the stop bit, the receiver resumes looking for a falling edge on RxD.
Timer 1
Overflow
Timer 2
Overflow
1/2
SMOD 0 1
0
1
TCLK
RCLK ⁰
1
1/16
1/16
SAMPLE
1-To-0
DETECTOR
RXD
Write to
SBUF
TX START
TX CLOCK
Transmit Shift Register
1
Internal
Data Bus
0
STOP
PARIN
START
LOAD
SOUT
CLOCK
TXD
TX SHIFT
Serial
Controllor ^TI
RX CLOCK
RI
Serial Interrupt
TX START
LOAD SBUF
RX SHIFT
Read SBUF
BIT
DETECTOR
CLOCK PAROUT
SBUF
SIN
D8
RB8
Receive Shift Register
Internal
Data Bus
Figure 16-2 Serial Port Mode 1
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Publication Release Date: December 14, 2007
Revision A3.0