W79E217A Datasheet, PDF (146/207 Pages) Winbond – 8-bit Microcontroller

Preliminary W79E217A Data Sheet
17.2.3 Control Register, I2CON
The CPU can read from and write to this 8-bit, directly addressable SFR. Two bits are affected by
hardware: the SI bit is set when the I2C hardware requests a serial interrupt, and the STO bit is
cleared when a STOP condition is present on the bus. The STO bit is also cleared when ENS = "0".
ENS
I2C serial function block enable bit. When ENS=1 the I2C serial function enables. The
port latches of SDA1 and SCL1 must be set to logic high.
STA
I2C START Flag. Setting STA to logic 1 to enter master mode, the I2C hardware sends a
START or repeat START condition to bus when the bus is free.
STO
I2C STOP Flag. In master mode, setting STO to transmit a STOP condition to bus then
I2C hardware will check the bus condition if a STOP condition is detected this flag will be
cleared by hardware automatically. In a slave mode, setting STO resets I2C hardware to
the “not addressed slave mode”.
SI
I2C Port 1 Interrupt Flag. When a new SIO state is present in the S1STA register, the SI
flag is set by hardware, and if the EA and EI2C1 bits are both set, the I2C1 interrupt is
requested. SI must be cleared by software.
AA
Assert Acknowledge control bit. When AA=1 prior to address or data received, an
acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on
the SCL line when; 1.) A slave is acknowledging the address sent from master, 2.) The
receiver devices are acknowledging the data sent by transmitter. When AA=0 prior to
address or data received, a not acknowledged (high level to SDA) will be returned during
the acknowledge clock pulse on the SCL line.
I2CIN
By default it is zero and input are allows to come in through SDA pin. As when it is 1 input
is disallow and to prevent leakage current. During Power-Down mode input is disallow.
17.2.4 Status Register, I2STATUS
I2STATUS is an 8-bit read-only register. The three least significant bits are always 0. The five most
significant bits contain the status code. There are 23 possible status codes. When I2STATUS contains
F8H, no serial interrupt is requested. All other I2STATUS values correspond to defined I2C ports
states. When each of these states is entered, a status interrupt is requested (SI = 1). A valid status
code is present in I2STATUS one machine cycle after SI is set by hardware and is still present one
machine cycle after SI has been reset by software.
In addition, state 00H stands for a Bus Error. A Bus Error occurs when a START or STOP condition is
present at an illegal position in the format frame. Examples of illegal positions are during the serial
transfer of an address byte, a data byte or an acknowledge bit.
17.2.5 I2C Clock Baud Rate Control, I2CLK
The data baud rate of I2C is determines by I2CLK register when I2C port is in a master mode. It is not
important when I2C port is in a slave mode. In the slave modes, SIO will automatically synchronize
with any clock frequency up to 400 KHz from master I2C device.
The data baud rate of I2C setting conforms to the following equation.
Data Baud Rate of I2C = F_CPU / (I2CLK + 1), where F_CPU = F_OSC/4.
For example, if F_OSC=16MHz, the I2CLK=40(28H), the data baud rate of I2C = (16MHz/4)/(40+1) =
97.56K bits/sec.
17.2.6 I2C Time-out Counter, I2Timer
In W79E217, the I2C logic block provides a 14-bit timer-out counter that helps user to deal with bus
pending problem. When SI is cleared user can set ENTI=1 to start the time-out counter. If I2C bus is
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Publication Release Date: December 14, 2007
Revision A3.0