W79E217A Datasheet, PDF (159/207 Pages) Winbond – 8-bit Microcontroller

Preliminary W79E217A Data Sheet
Figure 18-5: Master Mode Transmission (CPOL = 1, CPHA = 1)
18.3.2 Slave Mode
When in slave mode, the SPCLK pin becomes input and it will be clock by another master SPI device.
The SS pin also becomes input. Similarly, before data transmissions occurs, and remain low until the
transmission completed. If SS goes high, the SPI is forced into idle state. If the SS is forced to high at
the middle of transmission, the transmission will be aborted and the receiving shifter buffer will be high
and goes into idle states.
Data flows from master to slave on MOSI pin and flows from slave to master on MISO pin. The SPDR
is used when transmitting or receiving data on the serial bus. Only a write to this register initiates
transmission or reception of a byte, and this only occurs in the master device. At the completion of
transferring a byte of data, the SPIF status bit is set in both the master and slave devices.
A read of the SPDR is actually a read of a buffer. To prevent an overrun and the loss of the byte that
caused the overrun, the first SPIF must be cleared by the time a second transfer of data from the shift
register to the read buffer is initiated.
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Publication Release Date: December 14, 2007
Revision A3.0