W79E217A Datasheet, PDF (163/207 Pages) Winbond – 8-bit Microcontroller

Preliminary W79E217A Data Sheet
Figure 18-9: Slave Mode Transmission (CPOL = 1, CPHA = 1)
18.3.3 Slave select
The slave select ( SS ) input of a slave device must be externally asserted before a master device can
exchange data with the slave device. SS must be low before data transactions and must stay low for
the duration of the transaction. The SS line of the master must be held high. The other three lines are
dedicated to the SPI whenever the serial peripheral interface is on.
The state of the master and slave CPHA bits affects the operation of SS . CPHA settings should be
identical for master and slave. When CPHA = 0, the shift clock is the OR of SS with SPCLK. In this
clock phase mode, SS must go high between successive characters in an SPI message. When
CPHA = 1, SS can be left low between successive SPI characters. In cases where there is only one
SPI slave MCU, its SS line can be tied to VSS as long as only CPHA = 1 clock mode is used.
18.3.4 /SS output
Available in master mode only, SS output is enabled with the SSOE bit in the SPCR register and
DRSS bit in the SPSR register. The SS output pin is connected to the SS input pin of the slave
device. The SS output automatically goes low for each transmission when selecting external device
and it goes high during each idling state to deselect external devices.
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Publication Release Date: December 14, 2007
Revision A3.0