W79E217A Datasheet, PDF (72/207 Pages) Winbond – 8-bit Microcontroller

Preliminary W79E217A Data Sheet
8. INSTRUCTION SET
The W79E217 executes all the instructions of the standard 8051/52 family. The operations of these
instructions, as well as their effects on flag and status bits, are exactly the same. However, the timing
of these instructions is different in two ways. Firstly, the W79E217 machine cycle is four clock periods,
while the standard-8051/52 machine cycle is twelve clock periods. Secondly, the W79E217 can fetch
only once per machine cycle (i.e., four clocks per fetch), while the standard 8051/52 can fetch twice
per machine cycle (i.e., six clocks per fetch).
The timing differences create an advantage for the W79E217. There is only one fetch per machine
cycle, so the number of machine cycles is usually equal to the number of operands in the instruction.
(Jumps and calls do require an additional cycle to calculate the new address.) As a result, the
W79E217 reduces the number of dummy fetches and wasted cycles, and therefore improves overall
efficiency, compared to the standard 8051/52.
OP-CODE
HEX
CODE
BYTES
W79E217
MACHINE
CYCLE
W79E217
CLOCK
CYCLES
8032
CLOCK
CYCLES
W79E217 VS.
8032 SPEED
RATIO
NOP
00
1
1
4
12
3
ADD A, R0
28
1
1
4
12
3
ADD A, R1
29
1
1
4
12
3
ADD A, R2
2A
1
1
4
12
3
ADD A, R3
2B
1
1
4
12
3
ADD A, R4
2C
1
1
4
12
3
ADD A, R5
2D
1
1
4
12
3
ADD A, R6
2E
1
1
4
12
3
ADD A, R7
2F
1
1
4
12
3
ADD A, @R0
26
1
1
4
12
3
ADD A, @R1
27
1
1
4
12
3
ADD A, direct
25
2
2
8
12
1.5
ADD A, #data
24
2
2
8
12
1.5
ADDC A, R0
38
1
1
4
12
3
ADDC A, R1
39
1
1
4
12
3
ADDC A, R2
3A
1
1
4
12
3
ADDC A, R3
3B
1
1
4
12
3
ADDC A, R4
3C
1
1
4
12
3
ADDC A, R5
3D
1
1
4
12
3
ADDC A, R6
3E
1
1
4
12
3
ADDC A, R7
3F
1
1
4
12
3
ADDC A, @R0
36
1
1
4
12
3
ADDC A, @R1
37
1
1
4
12
3
ADDC A, direct
35
2
2
8
12
1.5
- 72 -
Publication Release Date: December 14, 2007
Revision A3.0