W79E217A Datasheet, PDF (122/207 Pages) Winbond – 8-bit Microcontroller

Preliminary W79E217A Data Sheet
14.10 Smart Fault Detector
This is a brake detection logic that is new to support external brake conditions that already exist. A
dedicated SFR FSPLT is added for this function. The SFR consists of smart fault detector control and
status bits. It basically consists of a clock divider, 8 bits counter, comparator and 4 selectable compare
values. The following diagram show the general block diagram.
Figure 14-25: Smart Fault Detector
The smart fault detector is enabled when bit LSBD = 1 (FSPLT.0). This logic detects low level brake
pin. The 8 bits counter is enabled by SFCEN bit located in SFR FSPLT.3. The counter is clock by
Fosc divider selectable by SFP1-0 control bits (FSPLT.5-4). The comparator compares the 8 bits
counter value with the compare value selectable with SCMP1-0 (FSPLT1-0).
Upon initial detection of low level at brake pin, the 8 bits counter will be active. This will cause the
counter to increment. While the counter is active and there is high level detected at brake pin, the
counter will decrement. See next figure for timing diagram. When the counter value reaches compare
value, BKF will be asserted.
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Publication Release Date: December 14, 2007
Revision A3.0