W79E217A Datasheet, PDF (46/207 Pages) Winbond – 8-bit Microcontroller

Preliminary W79E217A Data Sheet
SERIAL PORT CONTROL 1
Bit:
7
6
5
4
3
2
1
0
SM0_1/FE_1 SM1_1 SM2_1 REN_1 TB8_1
RB8_1
TI_1
RI_1
Mnemonic: SCON1
Address: C0h
BIT NAME
FUNCTION
Serial Port 1 mode select bit 0 or Framing Error Flag: This bit is controlled by the
7
SM0_1/ ^{SMOD0 bit in the PCON register.}
FE_1 (SM0) See table below.
(FE) This bit indicates an invalid stop bit. It must be manually cleared by software.
6 SM1_1 Serial Port 1 mode select bit 1. See table below.
Serial Port Clock or Multi-Processor Communication.
(Mode 0) This bit controls the serial port clock. If set to zero, the serial port runs at a
divide-by-12 clock of the oscillator. This is compatible with the standard 8051/52. If
set to one, the serial clock is a divide-by-4 clock of the oscillator.
5 SM2_1
(Mode 1) If SM2_1 is set to one, RI_1 is not activated if a valid stop bit is not
received.
(Modes 2 / 3) This bit enables multi-processor communication. If SM2_1 is set to
one, RI_1 is not activated if RB8_1, the ninth data bit, is zero.
Receive enable:
4 REN_1 1: Enable serial reception.
0: Disable serial reception.
3 TB8_1 (Modes 2 / 3) This is the 9th bit to transmit. This bit is set by software.
(Mode 0) No function.
2 RB8_1 (Mode 1) If SM2_1 = 0, RB8_1 is the stop bit that was received.
(Modes 2 / 3) This is the 9th bit that was received.
Transmit interrupt flag: This flag is set by the hardware at the end of the 8th bit in
1 TI_1 mode 0 or at the beginning of the stop bit in the other modes during serial
transmission. This bit must be cleared by software.
Receive interrupt flag: This flag is set by the hardware at the end of the 8th bit in
0 RI_1 mode 0 or halfway through the stop bits in the other modes during serial reception.
However, SM2_1 can restrict this behavior. This bit can only be cleared by software.
SM1_1, SM0_1: Mode Select bits:
SM0_1 SM1_1 MODE
DESCRIPTION
0
0
0
Synchronous
0
1
1
Asynchronous
1
0
2
Asynchronous
1
1
3
Asynchronous
LENGTH
8
10
11
11
BAUD RATE
Tclk divided by 4 or 12
Variable
Tclk divided by 32 or 64
Variable
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Publication Release Date: December 14, 2007
Revision A3.0