W79E217A Datasheet, PDF (134/207 Pages) Winbond – 8-bit Microcontroller

Preliminary W79E217A Data Sheet
15.1.1 Compare Mode
Timer 3 can be configured for compare mode. The compare mode is enabled by setting the CMP/RL3
bit to 1 in the T3CON register. RCAP3 will serves as a compare register. As Timer 3 counting up,
upon matching with RCAP3 value, TF3 will be set (which will generate an interrupt request if enable
Timer 3 interrupt ET3 is enabled) and the timer reload from 0 and starts counting again.
15.1.2 Reload Mode
Timer 3 can be also be configured for reload mode. The reload mode is enabled by clearing the
CMP/RL3 bit to 0 in the T3CON register. In this mode, RCAP serves as a reload register. When timer
3 overflows, a reload is generated that causes the contents of the RCAP3L and RCAP3H registers to
be reloaded into the TL3 and TH3 registers, if ENLD is set. TF3 flag is set, and interrupt request is
generated if enable Timer 3 interrupt ET3 is enabled. However, if ENLD = 0, timer 3 will be reload with
0, and count up again.
Alternatively, other reload source is also possible by the input capture pins by configuring the CCLD
[1:0] bit. If the ICENx bit is set, then a trigger of external IC0, IC1 or IC2 pin (respectively) will also
cause a reload. This action also sets the CPTF0, CPTF1 or CPTF2 flag bit in SFR CAPCON1,
respectively.
15.2 Quadrature Encoder Interface (QEI)
The Quadrature Encoder Interface (QEI) decodes speed of rotation and motion sensor information. It
can be used in any application that uses quadrature encoder for feedback. The QEI block supports the
features as below:
z Two QEI phase inputs: QEA and QEB.
z 16-bit Up/Down Pulse Counter (PLSCNT) with 16-bit read access latched buffer (PCNT).
z Four pulse counter update modes:
　 − Mode0: x4 free-counting mode.
　 − Mode1: x2 free-counting mode.
　 − Mode2: x4 compare-counting mode.
　 − Mode3: x2 compare-counting mode.
z Three interrupt sources:
　 − Pulse counter interrupt (CPTF0/QEIF).
　 − Direction index of motion detection with direction interrupt (CPTF1/DIRF).
　 − Input Capture 2 interrupt (CPTF2).
z The three 16-bit SFRs in QEI share the same addresses with the capture counter registers.
INPUT CAPTURE MODE
QEI MODE
Capture0 Counter Register
(CCH0, CCL0)
Pulse Read Counter Register
(PCNTH, PCNTL)
Capture1 Counter Register
(CCH1, CCL1)
Pulse Counter Register
(PLSCNTH, PLSCNTL)
Capture2 Counter Register
(CCH2, CCL2)
Maximum Counter Register
(MAXCNTH, MAXCNTL)
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Publication Release Date: December 14, 2007
Revision A3.0