W79E217A Datasheet, PDF (147/207 Pages) Winbond – 8-bit Microcontroller

Preliminary W79E217A Data Sheet
pended too long to get any valid signal from devices on bus, the time-out counter overflows cause
TIF=1 to request an I2C interrupt. The I2C interrupt is requested in the condition of either SI=1 or
TIF=1. Flags SI and TIF must be cleared by software.
17.2.7 I2C Maskable Slave Address
This register enables the Automatic Address Recognition feature of the I2C. When a bit in the
I2CSADEN is set to 1, the same bit location in I2CSADDR1 will be compared with the incoming serial
port data. When I2CSADEN.n is 0, then the bit becomes a don't-care in the comparison. This register
enables the Automatic Address Recognition feature of the I2C. When all the bits of I2CSADEN are 0,
interrupt will occur for any incoming address.
Fosc
0
1/4
DIV4
Enable
1
ENS1
ENTI
14-bits Counter
Clear Counter
TIF
SI
To I2C Interrupt
SI
Figure 17-3: I2C Time-out Block Diagram
17.3 Modes of Operation
The on-chip I2C ports support five operation modes, Master transmitter, Master receiver, Slave
transmitter, Slave receiver, and GC call.
In a given application, I2C port may operate as a master or as a slave. In the slave mode, the I2C port
hardware looks for its own slave address and the general call address. If one of these addresses is
detected, and if the slave is willing to receive or transmit data from/to master(by setting the AA bit),
acknowledge pulse will be transmitted out on the 9^th clock, hence an interrupt is requested on both
master and slave devices if interrupt is enabled. When the microcontroller wishes to become the bus
master, the hardware waits until the bus is free before the master mode is entered so that a possible
slave action is not interrupted. If bus arbitration is lost in the master mode, I2C port switches to the
slave mode immediately and can detect its own slave address in the same serial transfer.
17.3.1 Master Transmitter Mode
Serial data output through SDA while SCL outputs the serial clock. The first byte transmitted contains
the slave address of the receiving device (7 bits) and the data direction bit. In this case the data
direction bit (R/W) will be logic 0, and we say that a “W” is transmitted. Thus the first byte transmitted
is SLA+W. Serial data is transmitted 8 bits at a time. After each byte is transmitted, an acknowledge
bit is received. START and STOP conditions are output to indicate the beginning and the end of a
serial transfer.
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Publication Release Date: December 14, 2007
Revision A3.0