W79E217A Datasheet, PDF (23/207 Pages) Winbond – 8-bit Microcontroller

Preliminary W79E217A Data Sheet
Continued
SYMBOL DEFINITION
DPH
DPL
SP
DATA POINTER HIGH
DATA POINTER LOW
STACK POINTER
P0
PORT 0
ADDR MSB
ESS LSB
83H DPH.7
82H DPL.7
81H SP.7
80H
(87)
INT5
DPH.6
DPL.6
SP.6
(86)
INT4
DPH.5
DPL.5
SP.5
(85)
INT3
BIT_ADDRESS,
DPH.4
DPL.4
SP.4
(84)
INT2
DPH.3
DPL.3
SP.3
(83)
/SS
DPH.2
DPL.2
SP.2
(82)
SPCLK
DPH.1
DPL.1
SP.1
(81)
MOSI
SYMBOL _RESET
DPH.0
DPL.0
SP.0
(80)
MISO
0000 0000B
0000 0000B
0000 0111B
1111 1111B
Table 7-2: Special Function Registers
PORT 0
Bit:
7
P0.7
6
P0.6
5
P0.5
4
P0.4
3
P0.3
2
P0.2
1
P0.1
0
P0.0
Mnemonic: P0
Address: 80h
Port 0 is an open-drain 8-bit bi-directional I/O port. As an alternate function Port 0 can function as the
multiplexed address/data bus to access off-chip memory. During the time when ALE is high, the LSB
of a memory address is presented. When ALE is low, the port transits to a bi-directional data bus. This
bus is used for reading external ROM and for reading or writing external RAM memory or peripherals.
When used as a memory bus, the port provides active high drivers. The reset condition of Port 0 is tri-
state. Pull-up resistors are required when using Port 0 as an I/O port.
BIT
NAME
0 P0.0
1 P0.1
2 P0.2
3 P0.3
4 P0.4
5 P0.5
6 P0.6
7 P0.7
FUNCTION
MISO: SPI Master In Slave Out.
MOSI: SPI Master Out Slave In.
SPCLK: SPI Clock.
/SS: Slave Select.
INT2: External Interrupt 2.
INT3: External Interrupt 3.
INT4: External Interrupt 4.
INT5: External Interrupt 5.
STACK POINTER
Bit:
7
6
5
4
3
2
1
0
SP.7
SP.6
SP.5
SP.4
SP.3
SP.2
SP.1
SP.0
Mnemonic: SP
Address: 81h
The Stack Pointer stores the Scratch-pad RAM address where the stack begins. In other words it
always points to the top of the stack.
DATA POINTER LOW
Bit:
7
6
5
4
3
2
1
0
DPL.7
DPL.6
DPL.5
DPL.4
DPL.3
DPL.2
DPL.1
DPL.0
Mnemonic: DPL
This is the low byte of the standard 8032 16-bit data pointer.
Address: 82h
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Publication Release Date: December 14, 2007
Revision A3.0