W79E217A Datasheet, PDF (117/207 Pages) Winbond – 8-bit Microcontroller

Preliminary W79E217A Data Sheet
14.8 Center Aligned PWM (up/down counter)
1. 12-bit up counter matches PWMP
2. Update new duty cycle register (PWM0,2,4 and 6) if Load=1
3. Update new PWM period register (PWMP) if Load=1
PWMP (new)
PWMP (old)
PWM0 (new)
PWM0 (old)
PWM0
waveform
PWM period
PWM period
New PWM0
is written
New PWMP
is written
Figure 14-20: Center-Aligned Mode
Center-aligned PWM signals are produced by the module when the PWM time base is configured in
an Up/Down Counting mode (see Figure 14-20). The counter will start counting-up from 0 to match the
value of PWM0 (old); this will cause the toggling of the PWM0 output to low. The CPU reset states
determine the starts value of PWM0 waveform at starts of counter lies on the polarity setting located in
the Option bits. At this time the new PWM0 is written to the register. Counter continue to count and
match with the PWMP (old). Upon reaching this states counter is configured automatically to down
counting and toggle the PWM0 output when counter matches the PWM0 (old) value. Interrupt request
when up/down counter underflow. Once the counter reaches 0 it will update the duty cycle register
with Load = 1. Up-counting is continues with the matching at PWM0 (new) follow by a low toggle at the
PWM0 output. By this time the PWMP buffer is still consist of the PWMP (old) value. A new PWMP is
written. So the counter will still matches with this value and continues with down counting and
matched the PWM0 (new) and toggle the PWM0 output.
Again updates on the PWM period register is reflected on the 3^rd cycle of the diagram by starts
counting from 0 to match the PWM0 (new) and toggle at the PWM0 output to low. Counter is
continuing up-counting, upon reaching the PWMP (new) it is matched. Then counter is down counting
automatically to match at the PWM0 (new) to get a toggle high at PWM0 output.
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Publication Release Date: December 14, 2007
Revision A3.0