W79E217A Datasheet, PDF (145/207 Pages) Winbond – 8-bit Microcontroller

Preliminary W79E217A Data Sheet
SYMBOL DEFINITION
I2TIMER
I2C Timer Counter
Register
I2CLK I2C Clock Rate
I2STATUS I2C Status Register
I2DAT I2C Data
I2ADDR I2C Slave Address
I2CON I2C Control Register
I2CSADEN
I2C Maskable
Address
Slave
ADDRESS
MSB BIT_ADDRESS, SYMBOL LSB
RESET
EFH
EEH
EDH
ECH
EAH
E9H
F6H
-
-
-
-
-
ENTI DIV4 TIF
xxxx x000B
I2CLK.7
I2CLK.6
I2CLK.5
I2CLK.4
I2CLK.3
I2CLK.2
I2CLK.1
I2CLK.0
0000
0000B
I2STAT
US.7
I2STAT
US.6
I2STAT
US.5
I2STAT
US.4
I2STAT
US.3
-
-
-
1111
1000B
I2DAT.7
I2DAT.6
I2DAT.5
I2DAT.4
I2DAT.3
I2DAT.2
I2DAT.1
I2DAT.0
0000
0000B
ADDR.7 ADDR.6 ADDR.5 ADDR.4 ADDR.3 ADDR.2 ADDR.1 GC
0000
0000B
-
ENS STA STO SI
AA
I2CIN -
x000 000xB
I2CSAD I2CSAD I2CSAD I2CSAD I2CSAD I2CSAD I2CSAD I2CSAD 1111
EN.7 EN.6 EN.5 EN.4 EN.3 EN.2 EN.1 EN.0 1110B
Table 17-1: Control Registers of I2C Ports
17.2.1 Slave Address Registers, I2ADDR
I2C port is equipped with one slave address register. The contents of the register are irrelevant when
I2C is in master mode. In the slave mode, the seven most significant bits must be loaded with the
MCU’s own slave address. The I2C hardware will react if the contents of I2ADDR are matched with
the received slave address.
The I2C ports support the “General Call” function. If the GC bit is set the I2C port1 hardware will
respond to General Call address (00H). Clear GC bit to disable general call function.
When GC bit is set, the device is in slave mode which can receive the General Call address(00H) sent
by Master on the I2C bus. This special slave mode is referred to as GC mode.
17.2.2 Data Register, I2DAT
This register contains a byte of serial data to be transmitted or a byte which has just been received.
The CPU can read from or write to this 8-bit directly addressable SFR while it is not in the process of
shifting a byte. Data in I2DAT remains stable as long as SI is set. The MSB is shifted out first.While
data is being shifted out, data on the bus is simultaneously being shifted in; I2DAT always contains the
last data byte present on the bus. Thus, in the event of arbitration lost, the transition from master
transmitter to slave receiver is made with the correct data in I2DAT.
I2DAT and the acknowledge bit form a 9-bit shift register which shifts in or out an 8-bit byte, followed
by an acknowledge bit. The acknowledge bit is controlled by the hardware and cannot be accessed by
the CPU. Serial data is shifted into I2DAT on the rising edges of serial clock pulses on the SCL line.
When a byte has been shifted into I2DAT, the serial data is available in I2DAT, and the acknowledge
bit (ACK or NACK) is returned by the control logic during the ninth clock pulse. Serial data is shifted
out from I2DAT on the falling edges of SCL clock pulses, and is shifted into I2DAT on the rising edges
of SCL clock pulses.
I2C Data Register:
I2DAT.7 I2DAT.6 I2DAT.5 I2DAT.4 I2DAT.3 I2DAT.2 I2DAT.1 I2DAT.0
shifting direction
Figure 17-2: I2C Data Shift
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Publication Release Date: December 14, 2007
Revision A3.0