W79E217A Datasheet, PDF (88/207 Pages) Winbond – 8-bit Microcontroller

Preliminary W79E217A Data Sheet
10.2 Reset State
When the device is reset, most registers return to their initial state. The Watchdog Timer is disabled if
the reset source was a power-on reset. The port registers are set to FFh, which puts most of the port
pins in a high state and makes Port 0 float (as it does not have on-chip pull-up resistors). The Program
Counter is set to 0000h, and the stack pointer is reset to 07h. After this, the device remains in the
reset state as long as the reset conditions are satisfied.
Reset does not affect the on-chip RAM, however, so RAM is preserved as long as VDD remains
above approximately 2 V, the minimum operating voltage for the RAM. If VDD falls below 2 V, the
RAM contents are also lost. In either case, the stack pointer is always reset, so the stack contents are
lost.
The WDCON SFR bits are set/cleared in reset condition depends on the source of the reset. The
WDCON SFR is set to a 0x0x0xx0b on an external reset. WTRF is set to a 1 on a Watchdog timer
reset, but to a 0 on power on/down resets. WTRF is not altered by an external reset. POR is set to 1
by a power-on reset. EWT is cleared to 0 on a Power-on reset and unaffected by other resets. All the
bits in this SFR have unrestricted read access. POR, WDIF, EWT and RWT bits require Timed Access
(TA) procedure to write. The remaining bits have unrestricted write accesses. Please refer TA register
description. Table below lists the different reset values for WDCON due to different sources of reset.
WDCON
Watch-Dog
Control
D8H
x0xx 0000B External reset
(DF)
-
(DE)
POR
(DD)
-
(DC)
-
(DB) (DA) (D9)
WDIF WTRF EWT
(D8)
RWT
x0xx 0100B Watchdog
reset
x1xx 0000B Power on
reset
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Publication Release Date: December 14, 2007
Revision A3.0