W79E217A Datasheet, PDF (157/207 Pages) Winbond – 8-bit Microcontroller

Preliminary W79E217A Data Sheet
SPCLK Cycles
SPCLK (Output,
CPOL=1)
MOSI/MISO
/SS (output to slave)
1
2
3
4
5
6
7
8
2 MSB
6
5
4
3
2
1
LSB
1
4
SPIF
3
Master transfer in progress
Master writes to SPDR:
1. /SS asserted.
2. During master transmit, data is shifting out through MOSI.
During master receive, data is shifting in through MISO.
3. SPIF asserted at the end of transmission.
4. /SS negated.
Note:
When CPHA = 0, /SS output must go high between successive SPI characters.
When CPOL = 1, SPCLK idle high.
Figure 18-3: Master Mode Transmission (CPOL = 1, CPHA = 0)
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Publication Release Date: December 14, 2007
Revision A3.0