W79E217A Datasheet, PDF (87/207 Pages) Winbond – 8-bit Microcontroller

Preliminary W79E217A Data Sheet
10. RESET CONDITIONS
The user has several hardware related options for placing the W79E217 into reset condition. In
general, most register bits go to their reset value irrespective of the reset condition, but there are a few
flags whose state depends on the source of reset. The user can use these flags to determine the
cause of reset using software. There are three ways of putting the device into reset state. They are
External reset, Power-On Reset and Watchdog reset. In general, most registers return to their default
values regardless of the source of the reset, but a couple flags depend on the source. As a result, the
user can use these flags to determine the cause of the reset.
The rest of this section discusses the three causes of reset and then elaborates on the reset state.
10.1 Sources of reset
10.1.1 External Reset
The device samples the RST pin every machine cycle during state C4. The RST pin must be held high
for at least two machine cycles before the reset circuitry applies an internal reset signal. Thus, this
reset is a synchronous operation and requires the clock to be running.
The device remains in the reset state as long as RST is one and remains there up to two machine
cycles after RST is deactivated. Then, the device begins program execution at 0000h. There are no
flags associated with the external reset, but, since the other two reset sources do have flags, the
external reset is the cause if those flags are clear.
10.1.2 Power-On Reset (POR)
If the power supply falls below V_rst, the device goes into the reset state. When the power supply
returns to proper levels, the device performs a power-on reset and sets the POR flag. The software
should clear the POR flag, or it will be difficult to determine the source of future resets.
10.1.3 Watchdog Timer Reset
The Watchdog Timer is a free-running timer with programmable time-out intervals. The program must
clear the Watchdog Timer before the time-out interval is reached to restart the count. If the time-out
interval is reached, an interrupt flag is set. 512 clocks later, if the Watchdog Reset is enabled and the
Watchdog Timer has not been cleared, the Watchdog Timer generates a reset. The reset condition is
maintained by the hardware for two machine cycles, and the WTRF bit in WDCON is set. Afterwards,
the device begins program execution at 0000h.
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Publication Release Date: December 14, 2007
Revision A3.0