W79E217A Datasheet, PDF (67/207 Pages) Winbond – 8-bit Microcontroller

Preliminary W79E217A Data Sheet
BIT NAME
FUNCTION
7 SPIF
SPI Interrupt Complete Flag. SPIF is set upon completion of data transfer
between this device and external device or when new data has been received
and copied to the SPDR. If SPIF goes high, and if ESPI is set, a serial peripheral
interrupt is generated. When SPIF is set; it must be clear by software and
attempts to write SPDR are inhibited if SPIF set.
6 WCOL
Write Collision Flag. If a writer collision occurs on SPI bus, WCOL is set to high
by hardware. WCOL must be clear by software.
SPI overrun flag. SPIOVF is set if a new character is received before a
previously received character is read from SPDR. Once this bit is set it will
prevent SPDR register form excepting new data and must be cleared first before
5 SPIOVF _{any new data can be written. This flag is clear by software.}
0 = No overrun.
1 = Overrun detected.
4 MODF
SPI Mode Error Interrupt Status Flag. MODF is set when hardware detects mode
fault. This bit is cleared by software.
3 DRSS
Data Register Slave Select. Refer to above table in SPCR register.
2-0 -
Reserved.
Note: Bits WCOL, MODF and SPIF are cleared by software writing “0” to them.
SERIAL PERIPHERAL DATA I/O REGISTER
Bit:
7
6
5
4
SPD.7
SPD.6
SPD.5
SPD.4
3
SPD.3
2
SPD.2
1
SPD.1
0
SPD.0
Mnemonic: SPDR
Address: F5h
BIT NAME
7-0 SPD
FUNCTION
SPDR is used when transmitting or receiving data on serial bus. Only a write to
this register initiates transmission or reception of a byte, and this only occurs in
the master device. A read of the SPDR is actually a read of a buffer. To prevent
an overrun and the loss of the byte that caused the overrun, the first SPIF must
be cleared by the time a second transfer of data from the shift Register to the
read buffer is initiated.
I2C SLAVE ADDRESS MASK ENABLE
Bit:
7
6
5
I2CSADE I2CSADE I2CSADE
N.7
N.6
N.5
4
I2CSADE
N.4
3
I2CSADE
N.3
2
I2CSADE
N.2
1
I2CSADE
N.1
0
I2CSADE
N.0
Mnemonic: I2CSADEN
Address: F6h
BIT NAME
FUNCTION
This register enables the Automatic Address Recognition feature of the I2C.
When a bit in the I2CSADEN is set to 1, the same bit location in I2CSADDR1
will be compared with the incoming serial port data. When I2CSADEN.n is 0,
7-0 I2CSADEN the bit becomes don't care in the comparison. This register enables the
Automatic Address Recognition feature of the I2C. When all the bits of
I2CSADEN are 0, interrupt will occur for any incoming address. The default
value is 0xFE.
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Publication Release Date: December 14, 2007
Revision A3.0