W79E217A Datasheet, PDF (154/207 Pages) Winbond – 8-bit Microcontroller

Preliminary W79E217A Data Sheet
18. SERIAL PERIPHERAL INTERFACE (SPI)
18.1 General descriptions
This device consists of SPI block to support high speed serial communication. It’s capable of
supporting data transfer rates 1Mbit/s. This device’s SPI support the following features;
• Master and slave mode.
• Slave select output.
• Programmable serial clock’s polarity and phase.
• Receive double buffered data register.
• LSB first enable.
• Write collision detection.
• Transfer complete interrupt.
18.2 Block descriptions
The Figure 18-1 shows SPI block diagram. It provides an overview of SPI architecture in this device. The
main blocks of SPI are the register blocks, control logics, baud rate control and pin control logics;
a. Shift register and read data buffer. It is single buffered in the transmit direction and double
buffered in the receive direction. Transmit data cannot be written to the shifter until the
previous transfer is complete. Receive logics consist of parallel read data buffer so the shifter
is free to accept a second data, as the first received data will be transferred to the read data
buffer.
b. SPI Control block. This provide control functions to configure the device for SPI enable,
master or slave, clock phase and polarity, LSB access first selection, and Slave Select output
enable.
c. Baud rate control. These control logics divide CPU clock to 4 different selectable clocks 1/8
(reserved), 1/32, 1/128 and 1/256. Its’ selection is controllable through SPR [1:0] bits.
SPR1
SPR0
DIVIDER
BAUD RATE
0
0
8
Reserved
0
1
32
1.03MHz
1
0
128
257.81KHz
1
1
256
128.91KHz
Table 18-1: SPI Baud Rate Selection (F_OSC @ 33MHz)
d. SPI registers. There are three SPI registers to support its operations, they are;
• SPI control registers (SPCR)
• SPI status registers (SPSR)
• SPI data register (SPDR)
These registers provide control, status, data storage functions and baud rate selection control.
Detail bits descriptions are found at SFR section. When using SPI pull-up must be apply at bit
PUP0 = 1.
e. Pin control logic. Controls behavior of SPI interface pins.
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Publication Release Date: December 14, 2007
Revision A3.0