W79E217A Datasheet, PDF (90/207 Pages) Winbond – 8-bit Microcontroller

Preliminary W79E217A Data Sheet
11.2 Priority Level Structure
There are four priority levels for the interrupts; highest, high, low and lowest. The other interrupt
source can be individually set to either high or low levels. Naturally, a higher priority interrupt cannot
be interrupted by a lower priority interrupt. However there exists a predefined hierarchy amongst the
interrupts themselves. This hierarchy comes into play when the interrupt controller has to resolve
simultaneous requests having the same priority level. This hierarchy is defined as shown below; the
interrupts are numbered starting from the highest priority to the lowest.
SOURCE
External Interrupt 0
Timer 0 Overflow
External Interrupt 1
Timer 1 Overflow
Serial Port
Timer 2 Overflow
A/D Converter
I2C Channel
Serial Port 1
SPI interrupt
External Interrupt 2
External Interrupt 3
External Interrupt 4
External Interrupt 5
PWM Period
PWM Brake
Timer 3 Overflow
Capture
Input/Direction
Interrupt/QEI
NVM Interrupt
Watchdog Timer
FLAG
VECTOR
ADDRESS
IE0
0003H
TF0
000BH
IE1
0013H
TF1
001BH
RI + TI
0023H
TF2 + EXF2
002BH
ADCI
0033H
I2C1 SI
003BH
RI_1 + TI_1
007BH
SPIF + MODF +
SPIOVF
0083H
IE2
0043H
IE3
004BH
IE4
0053H
IE5
005BH
PWMF
0073H
BKF
006BH
TF3
008BH
CPTF0/QEIF+
CPTF1/DIRF+
CPTF2
0093H
NVMF
009BH
WDIF
0063H
FLAG CLEARED BY
PRIORITY
LEVEL
Hardware, Follow the
inverse of pin
1(highest)
Hardware, software 2
Hardware, Follow the
inverse of pin
3
Hardware, software 4
Software
5
Software
6
Software
7
Software
8
Software
9
Software
10
Hardware, software 11
Hardware, software 12
Hardware, software 13
Hardware, software 14
Software
15
Software
16
Software
17
Software
18
Software
19
Software
20
Table 11- 1: Priority structure of interrupts
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Publication Release Date: December 14, 2007
Revision A3.0