W79E217A Datasheet, PDF (31/207 Pages) Winbond – 8-bit Microcontroller

Preliminary W79E217A Data Sheet
P4.1 BASE ADDRESS HIGH BYTE REGISTER
Bit:
7
6
5
4
3
2
1
0
A15
A14
A13
A12
A11
A10
A9
A8
Mnemonic: P41AH
Address: 97h
SERIAL PORT CONTROL
Bit:
7
6
5
4
3
2
1
0
SM0/FE SM1
SM2
REN
TB8
RB8
TI
RI
Mnemonic: SCON
Address: 98h
BIT NAME
FUNCTION
Serial Port mode select bit 0 or Framing Error Flag: This bit is controlled by the
7
SM0/FE
SMOD0 bit in the PCON register.
(SM0) See table below.
(FE) This bit indicates an invalid stop bit. It must be manually cleared by software.
6 SM1 Serial Port mode select bit 1. See table below.
Serial Port Clock or Multi-Processor Communication.
(Mode 0) This bit controls the serial port clock. If set to zero, the serial port runs at a
divide-by-12 clock of the oscillator. This is compatible with the standard 8051/52. If
5 SM2 set to one, the serial clock is a divide-by-4 clock of the oscillator.
(Mode 1) If SM2 is set to one, RI is not activated if a valid stop bit is not received.
(Modes 2 / 3) This bit enables multi-processor communication. If SM2 is set to one,
RI is not activated if RB8, the ninth data bit, is zero.
Receive enable:
4 REN 1: Enable serial reception.
0: Disable serial reception.
3 TB8 (Modes 2 / 3) This is the 9th bit to transmit. This bit is set by software.
(Mode 0) No function.
2 RB8 (Mode 1) If SM2 = 0, RB8 is the stop bit that was received.
(Modes 2 / 3) This is the 9th bit that was received.
Transmit interrupt flag: This flag is set by the hardware at the end of the 8th bit in
1
TI mode 0 or at the beginning of the stop bit in the other modes during serial
transmission. This bit must be cleared by software.
Receive interrupt flag: This flag is set by the hardware at the end of the 8th bit in
0
RI mode 0 or halfway through the stop bits in the other modes during serial reception.
However, SM2 can restrict this behavior. This bit can only be cleared by software.
SM1, SM0: Mode Select bits:
SM0 SM1 MODE
0
0
0
0
1
1
1
0
2
1
1
3
DESCRIPTION
Synchronous
Asynchronous
Asynchronous
Asynchronous
LENGTH
8
10
11
11
BAUD RATE
Tclk divided by 4 or 12
Variable
Tclk divided by 32 or 64
Variable
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Publication Release Date: December 14, 2007
Revision A3.0