W79E217A Datasheet, PDF (165/207 Pages) Winbond – 8-bit Microcontroller

Preliminary W79E217A Data Sheet
18.3.6 Programmable serial clock’s phase and polarity
The clock polarity CPOL control bit selects active high or active low SPCLK clock, and has no
significant effect on the transfer format. The clock phase CPHA control bit selects one of two different
transfer protocols by sampling data on odd numbered SPCLK edges or on even numbered SPCLK
edges. Thus, both these bits enable selection of four possible clock formats to be used by SPI system.
The clock phase and polarity should be identical for the master SPI device and the communicating
slave device.
When CPHA equals 0, the SS line must be negated and reasserted between each successive serial
byte. Also, if the slave writes data to the SPI data register (SPDR) while SS is low, a write collision
error results. When CPHA equals 1, the SS line can remain low between successive transfers. The
figures from Figure 18-2 to 18-9 show the SPI transfer format, with different CPOL and CPHA. When
CPHA = 0, data is sample on the first edge of SPCLK and when CPHA = 1 data is sample on the
second edge of the SPCLK. Prior to changing CPOL setting, SPE must be disabled first.
18.3.7 Receive double buffered data register
This device is single buffered in the transmit direction and double buffered in the receive direction.
This means that new data for transmission cannot be written to the shifter until the previous transfer is
complete; however, received data is transferred into a parallel read data buffer so the shifter is free to
accept a second serial byte.
As long as the first byte is read out of the read data buffer before the next byte is ready to be
transferred, no overrun condition occurs. If overrun occur, SPIOVF is set. Second byte serial data
cannot be transferred successfully into the data register during overrun condition and the data register
will remains the value of the previous byte. The figure below shows the receive data timing waveform
when overrun occur.
Figure 18-11: SPI Overrun Timing Waveform
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Publication Release Date: December 14, 2007
Revision A3.0