W79E217A Datasheet, PDF (13/207 Pages) Winbond – 8-bit Microcontroller

Preliminary W79E217A Data Sheet
6.3 Auxiliary SRAM
W79E217 has a 2 KB of data space SRAM which is read/write accessible and is memory mapped.
This on-chip SRAM is accessed by the MOVX instruction. There is no conflict or overlap among the
256 bytes scratch-pad memory and the 2 KB auxiliary sram as they use different addressing modes
and instructions. Access to the on-chip Data Memory is optional under software control. Set DMEO bit
of PMR SFR to 1 will enable the on-chip 2 KB MOVX SRAM and at the same time EnNVM bit must be
cleared as NVM memory uses the same instruction of MOVX. Refer to Table 6-3: W79E217 NVM page (n)
area definition table.
6.4 2-KB NVM Data Flash Memory
W79E217 2-KB NVM memory block shown in the diagram on Figure 6-1, shares the same address as
AUX-RAM address.
Due to overlapping of AUX-RAM, NVM data memory and external data memory physical address, the
following table is defined. EnNVM bit (NVMCON.5) will enable read access to NVM data memory
area. DME0 (PMR.0) will enable read access to AUX-RAM.
ENNVM
0
0
1
DME0
0
1
X
DATA MEMORY AREA
Enable External RAM read/write access by MOVX
Enable AUX-RAM read/write access by MOVX
Enable NVM data Memory read access by MOVX only. If EER or
EWR is set and NVM flash erase or write control is busy, to set
this bit read NVM data is invalid.
Table 6-1: Bits setting for MOVX access to Data Memory Area
Read
access
Write
access
ENNVM = 1
INSTRUCTIONS
NVM SIZE = SRAM (2K)
ADDR ≤ 2K
ADDR > 2K
MOVX A, @DPTR (Read)
MOVX A, @R0 (Read)
MOVX A, @R1 (Read)
MOVX @DPTR, A (Write)
MOVX @R0, A (Write)
MOVX @R1, A (Write)
NVM
NVM
NVM
NOP
NOP
NOP
Ext memory
NOP
NOP
Ext memory
NOP
NOP
Table 6-2: MOVX read/write access destination
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Publication Release Date: December 14, 2007
Revision A3.0