W79E217A Datasheet, PDF (16/207 Pages) Winbond – 8-bit Microcontroller

Preliminary W79E217A Data Sheet
6.4.1 Operation
User is required to enable EnNVM (NVMCON.5) bit for all NVM access (read/write/erase).
Before write data to NVM memory, the page must be erased. A page is erased by setting page
address which address will decode and enable page (n) on NVMADDRH and NVMADDRL, then set
EER (NVMCON.7) and EnNVM (NVMCON.5). The device will then automatic execute page erase.
When completed, NVMF will be set by hardware. NVMF should be cleared by software. Interrupt
request will be generated if ENVM (EIE1.5) is enabled. EER bit will be cleared by hardware when
erase is completed. The total erase time is about 5ms.
For write, user must set address and data to NVMADDRH/L and NVMDAT, respectively. And then set
EWR (NVMCON.6) and EnNVM (NVMCON.5) to enable data write. When completed, the device will
set NVMF flag. NVMF flag should be cleared by software. Similarly, interrupt request will be generated
if ENVM (EIE1.5) is enabled. The program time is about 50us.
The following shows some examples of NVM operations:
Read NVM data is by MOVX A,@DPTR/R0/R1 instruction:
A read exceed 2k will read the external address
Example1: DPTR=0x07FF, R0/R1 = 0xFF, XRAMAH=0x07, EnNVM=1
MOVX A,@DPTR Æ read NVM data at address 0x07FF
MOVX A,@R0 Æ read NVM data at address 0x07FF
MOVX A,@R1 Æ read NVM data at address 0x07FF
Example2: DPTR = 0x2000, EnNVM=1, DME0=0
MOVX A,@DPTR Æ read external RAM data at address 0x2000,
Erase NVM by SFR register:
Example1: NVMADDRH = 0x07, NVMADDRL = 0xF0, page 31 will be enabled. After set EER, the
page 31 will be erased.
Example2: NVMADDRH = 0x10, NVMADDRL = 0x00, invalid NVM erase instruction (address exceed
NVM boundary).
Write NVM by SFR register:
Example1: NVMADDRH = 0x07, NVMADDRL = 0xF0
After set EWR, data will be written to the NVM address = 0x07F0 location.
Example2: NVMADDRH = 0x10, NVMADDRL = 0x00, after set EWR, invalid NVM write instruction
(address exceed NVM boundary).
During erase, write is invalid. Likewise, during write, erase is invalid. An erase or write is invalid if
NVMF is not clear by software. A write to NVMADDRH and NVMADDRL is invalid during Erase or
Write, and a write to NVMDAT is invalid only during NVM write access.
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Publication Release Date: December 14, 2007
Revision A3.0