W79E217A Datasheet, PDF (114/207 Pages) Winbond – 8-bit Microcontroller

Preliminary W79E217A Data Sheet
14.7 Edge Aligned PWM (up-counter)
Figure 14-16: Edge-Aligned PWM
In edge-aligned PWM Output mode, the 12 bits counter will starts counting from 0 to match with the
value of the duty cycle PWM0 (old). When the match occurs, it will toggle the PWM0 output waveform
to low. After CPU resets, the value of PWM0 waveform at starts of counter depend on the polarity
setting located in the Option bits. At this point a new PWM0 (new) is written. The counter will continue
counting to match with the value of the period register, PWMP (old) and toggle the PWM0 waveform to
high. Please take note that PWM0 and PWMP is a double-buffered register used to set the duty cycle
and counting period for the PWM time base respectively. For the 1^st buffer it is accessible by user
while the 2^nd buffer holds the actual compare value used in the present period. Load bit must be set to
1 to enable the value to be loaded in to the 2^nd buffer register when counter underflow/match.
When the counter matches the PWMP (old) it will automatically update the new duty cycle register and
the counter will again starts counting upwards to match the value PWM0 (new). At this point it will
toggle the PWM0 waveform to low. New PWMP is written at this point. When the counter continues
counting to match the PWMP (old), again the PWM0 waveform will be toggle to high. The counter
starts counting from 0 again; at this point the value is PWM0 (new) and PWMP (new) to be match by
the counter and once the counter matches these values it will be toggle at the PWM output.
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Publication Release Date: December 14, 2007
Revision A3.0