W79E217A Datasheet, PDF (166/207 Pages) Winbond – 8-bit Microcontroller

Preliminary W79E217A Data Sheet
18.3.8 LSB first enable
By default, this device transfer the SPI data most significant bit first. This device provides a control bit
SPCR.LSBFE to allow support of transfer of SPI data in least significant bit first.
18.3.9 Write Collision detection
Write collision indicates that an attempt was made to write data to the SPDR while a transfer was in
progress. SPDR is not double buffered in the transmit direction, any writes to SPDR cause data to be
written directly into the SPI shift register. This write corrupts any transfer in progress, a write collision
error is generated (WCOL will be set). The transfer continues undisturbed, and the write data that
caused the error is not written to the shifter. A write collision is normally a slave error because a slave
has no control over when a master initiates a transfer. A master knows when a transfer is in progress,
so there is no reason for a master to generate a write-collision error, although the SPI logic can detect
write collisions in both master and slave devices. WCOL flag is clear by software.
18.3.10Transfer complete interrupt
This device consists of an interrupt flag at SPIF. This flag will be set upon completion of data transfer
with external device, or when a new data have been received and copied to SPDR. If interrupt is
enable (through ESPI), the SPI interrupt request will be generated, if global enable bit EA is also
enabled. SPIF is software clear.
18.3.11Mode Fault
Error arises in a multiple-master system when more than one SPI device simultaneously tries to be a
master. This error is called a mode fault.
When the SPI system is configured as a master and the /SS input line goes to active low, a mode fault
error has occurred — usually because two devices have attempted to act as master at the same time.
In cases where more than one device is concurrently configured as a master, there is a chance of
contention between two pin drivers. For push-pull CMOS drivers, this contention can cause permanent
damage. The mode fault mechanism attempts to protect the device by disabling the drivers. The
MSTR and SPE control bits in the SPCR associated with the SPI are cleared by hardware and an
interrupt is generated subject to masking by the ESPI control bit.
Other precautions may need to be taken to prevent driver damage. If two devices are made masters at
the same time, mode fault does not help protect either one unless one of them selects the other as
slave. The amount of damage possible depends on the length of time both devices attempt to act as
master.
MODF bit is set automatically by SPI hardware, if the MSTR control bit is set and the slave select input
pin becomes 0. This condition is not permitted in normal operation. In the case where /SS is set, it is
an output pin rather than being dedicated as the /SS input for the SPI system. In this special case, the
mode fault function is inhibited and MODF remains cleared. This flag is cleared by software.
The following shows the sample hardware connection and s/w flow for multi-master/slave
environment. It shows how s/w handles mode fault.
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Publication Release Date: December 14, 2007
Revision A3.0