W79E217A Datasheet, PDF (25/207 Pages) Winbond – 8-bit Microcontroller

Preliminary W79E217A Data Sheet
BIT NAME
7 SMOD
6 SMOD0
5-4 -
3-2 GF1-0
1 PD
0 IDL
FUNCTION
This bit doubles the serial port baud rate in mode 1, 2, and 3 when set to 1.
Framing Error Detection Enable. When SMOD0 is set to 1, then SCON.7
(SCON1.7) now indicates a Frame Error and acts as the FE (FE_1) flag. When
SMOD0 is 0, then SCON.7 (SCON1.7) acts as per the standard 8032 function.
Reserved.
These two bits are general purpose user flags.
Setting this bit causes the device to go into the POWERDOWN mode. In this
mode all the clocks are stopped and program execution is frozen.
Setting this bit causes the device to go into the IDLE mode. In this mode the
clock to the CPU is stopped, so program execution is frozen, but the clock to the
serial ports, timer, PWM, ADC, SPI and interrupt blocks is not stopped, and
these blocks continue operating unhindered.
TIMER CONTROL
Bit:
7
6
5
4
3
2
1
0
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Mnemonic: TCON
Address: 88h
BIT NAME
FUNCTION
7 TF1
Timer 1 Overflow Flag. This bit is set when Timer 1 overflows. It is cleared
automatically when the program does a timer 1 interrupt service routine.
Software can also set or clear this bit.
6 TR1
Timer 1 Run Control. This bit is set or cleared by software to turn timer/counter
on or off.
5 TF0
Timer 0 Overflow Flag. This bit is set when Timer 0 overflows. It is cleared
automatically when the program does a timer 0 interrupt service routine.
Software can also set or clear this bit.
4 TR0
Timer 0 Run Control. This bit is set or cleared by software to turn timer/counter
on or off.
3 IE1
Interrupt 1 Edge Detect Flag: Set by hardware when an edge/level is detected
on INT1. This bit is cleared by hardware when the service routine is vectored to
only if the interrupt was edge triggered. Otherwise it follows the inverse of the
pin.
2 IT1
Interrupt 1 Type Control. Set/cleared by software to specify falling edge/ low
level triggered external inputs.
1 IE0
Interrupt 0 Edge Detect Flag. Set by hardware when an edge/level is detected
on INT0. This bit is cleared by hardware when the service routine is vectored to
only if the interrupt was edge triggered. Otherwise it follows the inverse of the
pin.
0 IT0
Interrupt 0 Type Control: Set/cleared by software to specify falling edge/ low
level triggered external inputs.
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Publication Release Date: December 14, 2007
Revision A3.0