W79E217A Datasheet, PDF (141/207 Pages) Winbond – 8-bit Microcontroller

Preliminary W79E217A Data Sheet
16.3 Mode 2
In Mode 2, full-duplex asynchronous communication is used. Frames consist of eleven bits: one start
bit (0), eight data bits (LSB first), a programmable ninth bit (TB8) and a stop bit (0). When receiving,
the ninth bit is put into RB8. The baud rate is 1/16 or 1/32 of the oscillator frequency, as determined by
SMOD in PCON.
Transmission begins with a write to SBUF but is synchronized with the divide-by-16 counter, not the
write to SBUF. The start bit is put on TxD pin at C1 following the first roll-over of the divide-by-16
counter, and the next bit is placed on TxD at C1 following the next rollover. After all nine bits of data
are transmitted, the stop bit is transmitted. The TI flag is set in the next C1 state, or the 11th rollover of
the divide-by-16 counter after the write to SBUF.
Reception is enabled when REN is high, and the serial port starts receiving data when it detects a
falling edge on RxD. The falling-edge detector monitors the RxD line at 16 times the selected baud
rate. When a falling edge is detected, the divide-by-16 counter is reset to align the bit boundaries with
the rollovers of the counter. The 16 states of the counter divide the bit time into 16 slices. Bit detection
is done on a best-of-three basis using samples at the 8th, 9th and 10th counter states. If the first bit
after the falling edge is not 0, the start bit is invalid, reception is aborted, and the serial port resumes
looking for a falling edge on RxD. If a valid start bit is detected, the rest of the bits are shifted into
SBUF. After shifting in nine data bits, the stop bit is received. Then, if;
1. RI is 0, and
2. SM2 is 0 or the received stop bit is 1,
the stop bit goes into RB8, the eight data bits go into SBUF, and RI is set. Otherwise, the received
frame may be lost. In the middle of the stop bit, the receiver resumes looking for a falling edge on
RxD. The functional description is shown in the figure below.
Fosc/2
1/2
SMOD 0 1
1/16
1/16
SAMPLE
1-To-0
DETECTOR
Write to
SBUF
TX START
TX CLOCK
Transmit Shift Register
1
TB8
Internal
Data Bus
0
STOP
D8
PARIN
START ^SOUT
LOAD
CLOCK
TXD
TX SHIFT
Serial
Controllor ^TI
RX CLOCK
RI
Serial Interrupt
TX START
LOAD SBUF
RX SHIFT
Read SBUF
CLOCK PAROUT
SBUF
Internal
Data Bus
RXD
BIT
DETECTOR
SIN
D8
RB8
Receive Shift Register
Figure 16-3: Serial Port Mode 2
- 141 -
Publication Release Date: December 14, 2007
Revision A3.0