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TA1360ANG Datasheet, PDF (63/108 Pages) Toshiba Semiconductor – TOSHIBA Bipolar Linear Integrated Circuit Silicon Monolithic
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Note No.
Characteristics
P24 VSM gain
P25 VSM limit
TA1360ANG
SW1
B
B
Test Conditions
SW Mode
SW2 SW3 SW7
B
A
B
B
B
A
SW56
Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C)
ON 1. Input sine wave of FVSM frequency to TPA. Set #3 amplitude to 0.02 Vp-p.
2. Turn on SW54 and change VSM gain from minimum (001) to maximum (111). Measure #54 amplitude, V001,
V011, V100, V101, V110, and V111. Set input amplitude to 0.7 Vp-p, and VSM gain to OFF (000). Measure
TP54 amplitude V000.
3. Calculate the following equations.
GV000 = 20 × log (V000/0.7) [dB]
GV001 = 20 × log (V001/0.02) [dB]
GV010 = 20 × log (V010/0.02) [dB]
GV011 = 20 × log (V011/0.02) [dB]
GV100 = 20 × log (V100/0.02) [dB]
GV101 = 20 × log (V101/0.02) [dB]
GV110 = 20 × log (V110/0.02) [dB]
GV111 = 20 × log (V111/0.02) [dB]
ON 1. Input sine wave of frequency FVSM to TPA.
2. Set VSM gain to 111, and #3 amplitude to 0.7 Vp-p.
3. Turn on SW54 and measure TP54 amplitude VLU and VLD [Vp-p] as shown in the figure below.
VLU
VLD
63
2003-01-21
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