TA1360ANG Datasheet, PDF (56/108 Pages) Toshiba Semiconductor – TOSHIBA Bipolar Linear Integrated Circuit Silicon Monolithic

TA1360ANG
Note No.
Characteristics
P17 DC restoration rate correction
gain
SW1
B
Test Conditions
SW Mode
SW2 SW3 SW7
B
C
B
SW56
ON 1.
2.
3.
4.
5.
6.
Test Method (Test condition: V_CC = 9 V/2 V, Ta = 25 ± 3°C)
Set DC restoration rate correction point to minimum (000), DC restoration rate correction limit point to 80%
(11), and connect external power supply PS1 to #3.
Monitor DC level of #43 picture period. Set PS1 to V₃ + 0.7 V, and adjust uncolor so that DC level is + 0.7.
Set DC restoration correction rate to minimum (000), and measure V_DT1 and V_DT2 of V₃ [V] and V₃ + 0.1 V
as shown in the figure below.
Set #3 to V₃ + 0.1 V, DC restoration correction rate to maximum (111), and measure V_DT3.
Set DC restoration correction rate SW to less than 100 % (1), #3 to V₃ + 0.1 V, DC restoration correction rate
to maximum (111), and measure V_DT4.
Calculate ADT₁₀₀, ADT₁₃₅, and ADT₆₅ using following equations.
ADT₁₀₀ = (V_DT2 [V] − V_DT1 [V]) ÷ 0.1 [V]
ADT₁₃₅ = (V_DT3 [V] − V_DT1 [V]) ÷ 0.1 [V]
ADT₆₅ = 1 − ( (V_DT2 [V] − V_DT4 [V]) ÷ 0.1 [V])
V₃ [V]
Picture period
V_DT1
V₃ + 0.1 V
#43 waveform
V_DT2 V_DT3
V_DT4
56
2003-01-21